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| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2016-08-23 15:58:56 +0200 |
|---|---|---|
| committer | Scott Wood <oss@buserror.net> | 2016-09-25 02:38:53 -0500 |
| commit | 834e5a692120cc25c3935e8652a1989c2bc1c9e9 (patch) | |
| tree | 7b9707625fe89d567ceef4f6a8816807a3de5f3d /arch/powerpc | |
| parent | fff69fd03d1290297fcd039b07819fafa69ffc0a (diff) | |
| download | op-kernel-dev-834e5a692120cc25c3935e8652a1989c2bc1c9e9.zip op-kernel-dev-834e5a692120cc25c3935e8652a1989c2bc1c9e9.tar.gz | |
powerpc/8xx: use SPRN_EIE and SPRN_EID to enable/disable interrupts
The 8xx has two special registers called EID (External Interrupt
Disable) and EIE (External Interrupt Enable) for clearing/setting
EE in MSR. It avoids the three instructions set mfmsr/ori/mtmsr or
mfmsr/rlwinm/mtmsr and it avoids using a general register.
We just have to write something in the special register to change MSR EE
bit. So we write r0 into the register, regardless of r0 value.
Writing to one of those two special registers also set the MSR RI bit,
but this bit is only unset during beginning of exception prolog and end
of exception epilog. When executing C-functions MSR RI is always set.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc')
| -rw-r--r-- | arch/powerpc/include/asm/hw_irq.h | 6 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg.h | 2 | ||||
| -rw-r--r-- | arch/powerpc/include/asm/reg_8xx.h | 4 |
3 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h index c7d82ff..eba6041 100644 --- a/arch/powerpc/include/asm/hw_irq.h +++ b/arch/powerpc/include/asm/hw_irq.h @@ -155,6 +155,8 @@ static inline unsigned long arch_local_irq_save(void) unsigned long flags = arch_local_save_flags(); #ifdef CONFIG_BOOKE asm volatile("wrteei 0" : : : "memory"); +#elif defined(CONFIG_PPC_8xx) + wrtspr(SPRN_EID); #else SET_MSR_EE(flags & ~MSR_EE); #endif @@ -165,6 +167,8 @@ static inline void arch_local_irq_disable(void) { #ifdef CONFIG_BOOKE asm volatile("wrteei 0" : : : "memory"); +#elif defined(CONFIG_PPC_8xx) + wrtspr(SPRN_EID); #else arch_local_irq_save(); #endif @@ -174,6 +178,8 @@ static inline void arch_local_irq_enable(void) { #ifdef CONFIG_BOOKE asm volatile("wrteei 1" : : : "memory"); +#elif defined(CONFIG_PPC_8xx) + wrtspr(SPRN_EIE); #else unsigned long msr = mfmsr(); SET_MSR_EE(msr | MSR_EE); diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index 9dddabc..b320c8f 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -1249,6 +1249,8 @@ static inline void mtmsr_isync(unsigned long val) : "r" ((unsigned long)(v)) \ : "memory") #endif +#define wrtspr(rn) asm volatile("mtspr " __stringify(rn) ",0" : \ + : : "memory") extern void msr_check_and_set(unsigned long bits); extern bool strict_msr_control; diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h index 94d01f8..0197e12 100644 --- a/arch/powerpc/include/asm/reg_8xx.h +++ b/arch/powerpc/include/asm/reg_8xx.h @@ -25,6 +25,10 @@ #define SPRN_MD_RAM0 825 #define SPRN_MD_RAM1 826 +/* Special MSR manipulation registers */ +#define SPRN_EIE 80 /* External interrupt enable (EE=1, RI=1) */ +#define SPRN_EID 81 /* External interrupt disable (EE=0, RI=1) */ + /* Commands. Only the first few are available to the instruction cache. */ #define IDC_ENABLE 0x02000000 /* Cache enable */ |
