diff options
author | Geoff Levand <geoffrey.levand@am.sony.com> | 2006-06-19 20:33:29 +0200 |
---|---|---|
committer | Paul Mackerras <paulus@samba.org> | 2006-06-21 15:01:31 +1000 |
commit | 540270d82db943855538cea5d0c790e7e669dda0 (patch) | |
tree | e13b8194d8781b2f5d3bf6566a8d96ecc943f8f3 /arch/powerpc | |
parent | c01ea72a3b8abb7baa4291a1876b82599867035a (diff) | |
download | op-kernel-dev-540270d82db943855538cea5d0c790e7e669dda0.zip op-kernel-dev-540270d82db943855538cea5d0c790e7e669dda0.tar.gz |
[POWERPC] spufs: further abstract priv1 register access
To support muti-platform binaries the spu hypervisor accessor
routines must have runtime binding.
I removed the existing statically linked routines in spu.h
and spu_priv1_mmio.c and created new accessor routines in spu_priv1.h
that operate indirectly through an ops struct spu_priv1_ops.
spu_priv1_mmio.c contains the instance of the accessor routines
for running on raw hardware.
Signed-off-by: Geoff Levand <geoffrey.levand@am.sony.com>
Signed-off-by: Arnd Bergmann <arnd.bergmann@de.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc')
-rw-r--r-- | arch/powerpc/platforms/cell/setup.c | 4 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spu_base.c | 5 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spu_priv1_mmio.c | 104 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spufs/hw_ops.c | 1 | ||||
-rw-r--r-- | arch/powerpc/platforms/cell/spufs/switch.c | 1 |
5 files changed, 74 insertions, 41 deletions
diff --git a/arch/powerpc/platforms/cell/setup.c b/arch/powerpc/platforms/cell/setup.c index eb8ab9b..3d1831d 100644 --- a/arch/powerpc/platforms/cell/setup.c +++ b/arch/powerpc/platforms/cell/setup.c @@ -49,6 +49,7 @@ #include <asm/ppc-pci.h> #include <asm/irq.h> #include <asm/spu.h> +#include <asm/spu_priv1.h> #include "interrupt.h" #include "iommu.h" @@ -83,6 +84,9 @@ static void __init cell_setup_arch(void) { ppc_md.init_IRQ = iic_init_IRQ; ppc_md.get_irq = iic_get_irq; +#ifdef CONFIG_SPU_BASE + spu_priv1_ops = &spu_priv1_mmio_ops; +#endif cbe_regs_init(); diff --git a/arch/powerpc/platforms/cell/spu_base.c b/arch/powerpc/platforms/cell/spu_base.c index eb367dd..c3bb729 100644 --- a/arch/powerpc/platforms/cell/spu_base.c +++ b/arch/powerpc/platforms/cell/spu_base.c @@ -34,10 +34,15 @@ #include <asm/prom.h> #include <linux/mutex.h> #include <asm/spu.h> +#include <asm/spu_priv1.h> #include <asm/mmu_context.h> #include "interrupt.h" +const struct spu_priv1_ops *spu_priv1_ops; + +EXPORT_SYMBOL_GPL(spu_priv1_ops); + static int __spu_trap_invalid_dma(struct spu *spu) { pr_debug("%s\n", __FUNCTION__); diff --git a/arch/powerpc/platforms/cell/spu_priv1_mmio.c b/arch/powerpc/platforms/cell/spu_priv1_mmio.c index b265642..abe8a84 100644 --- a/arch/powerpc/platforms/cell/spu_priv1_mmio.c +++ b/arch/powerpc/platforms/cell/spu_priv1_mmio.c @@ -1,133 +1,155 @@ /* - * access to SPU privileged registers + * spu hypervisor abstraction for direct hardware access. + * + * (C) Copyright IBM Deutschland Entwicklung GmbH 2005 + * Copyright 2006 Sony Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ + #include <linux/module.h> #include <asm/io.h> #include <asm/spu.h> +#include <asm/spu_priv1.h> -void spu_int_mask_and(struct spu *spu, int class, u64 mask) +static void int_mask_and(struct spu *spu, int class, u64 mask) { u64 old_mask; old_mask = in_be64(&spu->priv1->int_mask_RW[class]); out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask); } -EXPORT_SYMBOL_GPL(spu_int_mask_and); -void spu_int_mask_or(struct spu *spu, int class, u64 mask) +static void int_mask_or(struct spu *spu, int class, u64 mask) { u64 old_mask; old_mask = in_be64(&spu->priv1->int_mask_RW[class]); out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask); } -EXPORT_SYMBOL_GPL(spu_int_mask_or); -void spu_int_mask_set(struct spu *spu, int class, u64 mask) +static void int_mask_set(struct spu *spu, int class, u64 mask) { out_be64(&spu->priv1->int_mask_RW[class], mask); } -EXPORT_SYMBOL_GPL(spu_int_mask_set); -u64 spu_int_mask_get(struct spu *spu, int class) +static u64 int_mask_get(struct spu *spu, int class) { return in_be64(&spu->priv1->int_mask_RW[class]); } -EXPORT_SYMBOL_GPL(spu_int_mask_get); -void spu_int_stat_clear(struct spu *spu, int class, u64 stat) +static void int_stat_clear(struct spu *spu, int class, u64 stat) { out_be64(&spu->priv1->int_stat_RW[class], stat); } -EXPORT_SYMBOL_GPL(spu_int_stat_clear); -u64 spu_int_stat_get(struct spu *spu, int class) +static u64 int_stat_get(struct spu *spu, int class) { return in_be64(&spu->priv1->int_stat_RW[class]); } -EXPORT_SYMBOL_GPL(spu_int_stat_get); -void spu_int_route_set(struct spu *spu, u64 route) +static void int_route_set(struct spu *spu, u64 route) { out_be64(&spu->priv1->int_route_RW, route); } -EXPORT_SYMBOL_GPL(spu_int_route_set); -u64 spu_mfc_dar_get(struct spu *spu) +static u64 mfc_dar_get(struct spu *spu) { return in_be64(&spu->priv1->mfc_dar_RW); } -EXPORT_SYMBOL_GPL(spu_mfc_dar_get); -u64 spu_mfc_dsisr_get(struct spu *spu) +static u64 mfc_dsisr_get(struct spu *spu) { return in_be64(&spu->priv1->mfc_dsisr_RW); } -EXPORT_SYMBOL_GPL(spu_mfc_dsisr_get); -void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr) +static void mfc_dsisr_set(struct spu *spu, u64 dsisr) { out_be64(&spu->priv1->mfc_dsisr_RW, dsisr); } -EXPORT_SYMBOL_GPL(spu_mfc_dsisr_set); -void spu_mfc_sdr_set(struct spu *spu, u64 sdr) +static void mfc_sdr_set(struct spu *spu, u64 sdr) { out_be64(&spu->priv1->mfc_sdr_RW, sdr); } -EXPORT_SYMBOL_GPL(spu_mfc_sdr_set); -void spu_mfc_sr1_set(struct spu *spu, u64 sr1) +static void mfc_sr1_set(struct spu *spu, u64 sr1) { out_be64(&spu->priv1->mfc_sr1_RW, sr1); } -EXPORT_SYMBOL_GPL(spu_mfc_sr1_set); -u64 spu_mfc_sr1_get(struct spu *spu) +static u64 mfc_sr1_get(struct spu *spu) { return in_be64(&spu->priv1->mfc_sr1_RW); } -EXPORT_SYMBOL_GPL(spu_mfc_sr1_get); -void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id) +static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id) { out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id); } -EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_set); -u64 spu_mfc_tclass_id_get(struct spu *spu) +static u64 mfc_tclass_id_get(struct spu *spu) { return in_be64(&spu->priv1->mfc_tclass_id_RW); } -EXPORT_SYMBOL_GPL(spu_mfc_tclass_id_get); -void spu_tlb_invalidate(struct spu *spu) +static void tlb_invalidate(struct spu *spu) { out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul); } -EXPORT_SYMBOL_GPL(spu_tlb_invalidate); -void spu_resource_allocation_groupID_set(struct spu *spu, u64 id) +static void resource_allocation_groupID_set(struct spu *spu, u64 id) { out_be64(&spu->priv1->resource_allocation_groupID_RW, id); } -EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_set); -u64 spu_resource_allocation_groupID_get(struct spu *spu) +static u64 resource_allocation_groupID_get(struct spu *spu) { return in_be64(&spu->priv1->resource_allocation_groupID_RW); } -EXPORT_SYMBOL_GPL(spu_resource_allocation_groupID_get); -void spu_resource_allocation_enable_set(struct spu *spu, u64 enable) +static void resource_allocation_enable_set(struct spu *spu, u64 enable) { out_be64(&spu->priv1->resource_allocation_enable_RW, enable); } -EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_set); -u64 spu_resource_allocation_enable_get(struct spu *spu) +static u64 resource_allocation_enable_get(struct spu *spu) { return in_be64(&spu->priv1->resource_allocation_enable_RW); } -EXPORT_SYMBOL_GPL(spu_resource_allocation_enable_get); + +const struct spu_priv1_ops spu_priv1_mmio_ops = +{ + .int_mask_and = int_mask_and, + .int_mask_or = int_mask_or, + .int_mask_set = int_mask_set, + .int_mask_get = int_mask_get, + .int_stat_clear = int_stat_clear, + .int_stat_get = int_stat_get, + .int_route_set = int_route_set, + .mfc_dar_get = mfc_dar_get, + .mfc_dsisr_get = mfc_dsisr_get, + .mfc_dsisr_set = mfc_dsisr_set, + .mfc_sdr_set = mfc_sdr_set, + .mfc_sr1_set = mfc_sr1_set, + .mfc_sr1_get = mfc_sr1_get, + .mfc_tclass_id_set = mfc_tclass_id_set, + .mfc_tclass_id_get = mfc_tclass_id_get, + .tlb_invalidate = tlb_invalidate, + .resource_allocation_groupID_set = resource_allocation_groupID_set, + .resource_allocation_groupID_get = resource_allocation_groupID_get, + .resource_allocation_enable_set = resource_allocation_enable_set, + .resource_allocation_enable_get = resource_allocation_enable_get, +}; diff --git a/arch/powerpc/platforms/cell/spufs/hw_ops.c b/arch/powerpc/platforms/cell/spufs/hw_ops.c index a13a8b5..ede2cac 100644 --- a/arch/powerpc/platforms/cell/spufs/hw_ops.c +++ b/arch/powerpc/platforms/cell/spufs/hw_ops.c @@ -32,6 +32,7 @@ #include <asm/io.h> #include <asm/spu.h> +#include <asm/spu_priv1.h> #include <asm/spu_csa.h> #include <asm/mmu_context.h> #include "spufs.h" diff --git a/arch/powerpc/platforms/cell/spufs/switch.c b/arch/powerpc/platforms/cell/spufs/switch.c index 85bea06..2dae062 100644 --- a/arch/powerpc/platforms/cell/spufs/switch.c +++ b/arch/powerpc/platforms/cell/spufs/switch.c @@ -46,6 +46,7 @@ #include <asm/io.h> #include <asm/spu.h> +#include <asm/spu_priv1.h> #include <asm/spu_csa.h> #include <asm/mmu_context.h> |