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authorMatt Weber <matthew.weber@rockwellcollins.com>2017-06-28 11:14:29 -0500
committerScott Wood <oss@buserror.net>2017-08-28 23:15:32 -0500
commita4e89ffb59235fd11d27107dea3efa4562ac0a12 (patch)
tree8a2e97f092315e36a01e89aa48893fcae219518b /arch/powerpc
parentd1d0d5ffb3006eaf9b5f41c89fe801e032cbbfe4 (diff)
downloadop-kernel-dev-a4e89ffb59235fd11d27107dea3efa4562ac0a12.zip
op-kernel-dev-a4e89ffb59235fd11d27107dea3efa4562ac0a12.tar.gz
powerpc/e6500: Update machine check for L1D cache err
This patch updates the machine check handler of Linux kernel to handle the e6500 architecture case. In e6500 core, L1 Data Cache Write Shadow Mode (DCWS) register is not implemented but L1 data cache always runs in write shadow mode. So, on L1 data cache parity errors, hardware will automatically invalidate the data cache but will still log a machine check interrupt. Signed-off-by: Ronak Desai <ronak.desai@rockwellcollins.com> Signed-off-by: Matthew Weber <matthew.weber@rockwellcollins.com> Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc')
-rw-r--r--arch/powerpc/kernel/traps.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index 675d5d2..410352a 100644
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -393,6 +393,7 @@ static inline int check_io_access(struct pt_regs *regs)
int machine_check_e500mc(struct pt_regs *regs)
{
unsigned long mcsr = mfspr(SPRN_MCSR);
+ unsigned long pvr = mfspr(SPRN_PVR);
unsigned long reason = mcsr;
int recoverable = 1;
@@ -434,8 +435,15 @@ int machine_check_e500mc(struct pt_regs *regs)
* may still get logged and cause a machine check. We should
* only treat the non-write shadow case as non-recoverable.
*/
- if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
- recoverable = 0;
+ /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
+ * is not implemented but L1 data cache always runs in write
+ * shadow mode. Hence on data cache parity errors HW will
+ * automatically invalidate the L1 Data Cache.
+ */
+ if (PVR_VER(pvr) != PVR_VER_E6500) {
+ if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
+ recoverable = 0;
+ }
}
if (reason & MCSR_L2MMU_MHIT) {
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