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authorAyman El-Khashab <ayman@elkhashab.com>2011-07-20 03:02:29 +0000
committerJosh Boyer <jwboyer@gmail.com>2011-08-11 13:51:18 -0400
commite7fa1d131472b1134d33aba56a83f8f7689f54fd (patch)
treecb728714ba8f2916c214ec9e8c9367bdfdb0a683 /arch/powerpc/sysdev/ppc4xx_pci.h
parent2f6bab96ef60dd87e0a17272f9f8a6ee12118d32 (diff)
downloadop-kernel-dev-e7fa1d131472b1134d33aba56a83f8f7689f54fd.zip
op-kernel-dev-e7fa1d131472b1134d33aba56a83f8f7689f54fd.tar.gz
powerpc/4xx: enable and fix pcie gen1/gen2 on the 460sx
Adds a register to the config space for the 460sx. Changes the vc0 detect to a pll detect. maps configuration space to test the link status. changes the setup to enable gen2 devices to operate at gen2 speeds. fixes mapping that was not correct for the 460sx. added bit definitions for the OMRxMSKL registers. Removed reserved bit that was set incorrectly in the OMR2MSKL register. tested on the 460sx eiger and custom board Signed-off-by: Ayman El-Khashab <ayman@elkhashab.com> Signed-off-by: Josh Boyer <jwboyer@gmail.com>
Diffstat (limited to 'arch/powerpc/sysdev/ppc4xx_pci.h')
-rw-r--r--arch/powerpc/sysdev/ppc4xx_pci.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/sysdev/ppc4xx_pci.h b/arch/powerpc/sysdev/ppc4xx_pci.h
index c39a134..32ce763 100644
--- a/arch/powerpc/sysdev/ppc4xx_pci.h
+++ b/arch/powerpc/sysdev/ppc4xx_pci.h
@@ -464,6 +464,18 @@
#define PECFG_POM2LAL 0x390
#define PECFG_POM2LAH 0x394
+/* 460sx only */
+#define PECFG_460SX_DLLSTA 0x3f8
+
+/* 460sx Bit Mappings */
+#define PECFG_460SX_DLLSTA_LINKUP 0x00000010
+#define DCRO_PEGPL_460SX_OMR1MSKL_UOT 0x00000004
+
+/* PEGPL Bit Mappings */
+#define DCRO_PEGPL_OMRxMSKL_VAL 0x00000001
+#define DCRO_PEGPL_OMR1MSKL_UOT 0x00000002
+#define DCRO_PEGPL_OMR3MSKL_IO 0x00000002
+
/* SDR Bit Mappings */
#define PESDRx_RCSSET_HLDPLB 0x10000000
#define PESDRx_RCSSET_RSTGU 0x01000000
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