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author | Takashi Iwai <tiwai@suse.de> | 2012-03-18 18:22:37 +0100 |
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committer | Takashi Iwai <tiwai@suse.de> | 2012-03-18 18:22:37 +0100 |
commit | cb3f2adc03ab055b19c677a6283523861fafebdd (patch) | |
tree | 59cfb6800f0635a4aec16c8e0da619f27e51ee79 /arch/powerpc/sysdev/fsl_pci.c | |
parent | 44c76a960a62fcc46cbcaa0a22a34e666a729329 (diff) | |
parent | 828006de1bddf83b6ecf03ec459c15f7c7c22db7 (diff) | |
download | op-kernel-dev-cb3f2adc03ab055b19c677a6283523861fafebdd.zip op-kernel-dev-cb3f2adc03ab055b19c677a6283523861fafebdd.tar.gz |
Merge branch 'topic/asoc' into for-linus
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
-rw-r--r-- | arch/powerpc/sysdev/fsl_pci.c | 53 |
1 files changed, 32 insertions, 21 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c index 3b61e8c..6073288 100644 --- a/arch/powerpc/sysdev/fsl_pci.c +++ b/arch/powerpc/sysdev/fsl_pci.c @@ -205,12 +205,12 @@ static void __init setup_pci_atmu(struct pci_controller *hose, if (paddr_hi == paddr_lo) { pr_err("%s: No outbound window space\n", name); - return ; + goto out; } if (paddr_lo == 0) { pr_err("%s: No space for inbound window\n", name); - return ; + goto out; } /* setup PCSRBAR/PEXCSRBAR */ @@ -357,6 +357,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose, (u64)hose->dma_window_size); } +out: iounmap(pci); } @@ -384,26 +385,36 @@ static void __init setup_pci_cmd(struct pci_controller *hose) void fsl_pcibios_fixup_bus(struct pci_bus *bus) { struct pci_controller *hose = pci_bus_to_host(bus); - int i; - - if ((bus->parent == hose->bus) && - ((fsl_pcie_bus_fixup && - early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) || - (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK))) - { - for (i = 0; i < 4; ++i) { + int i, is_pcie = 0, no_link; + + /* The root complex bridge comes up with bogus resources, + * we copy the PHB ones in. + * + * With the current generic PCI code, the PHB bus no longer + * has bus->resource[0..4] set, so things are a bit more + * tricky. + */ + + if (fsl_pcie_bus_fixup) + is_pcie = early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP); + no_link = !!(hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK); + + if (bus->parent == hose->bus && (is_pcie || no_link)) { + for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; ++i) { struct resource *res = bus->resource[i]; - struct resource *par = bus->parent->resource[i]; - if (res) { - res->start = 0; - res->end = 0; - res->flags = 0; - } - if (res && par) { - res->start = par->start; - res->end = par->end; - res->flags = par->flags; - } + struct resource *par; + + if (!res) + continue; + if (i == 0) + par = &hose->io_resource; + else if (i < 4) + par = &hose->mem_resources[i-1]; + else par = NULL; + + res->start = par ? par->start : 0; + res->end = par ? par->end : 0; + res->flags = par ? par->flags : 0; } } } |