diff options
| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2010-02-26 14:41:00 +1100 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2010-02-26 14:41:00 +1100 |
| commit | 874f2f997dbe041a6c6e509dae8656ed9022d65d (patch) | |
| tree | 61898165882041ef7f9beaf2ef6663a1a4d3c29a /arch/powerpc/platforms/85xx | |
| parent | 071c06cb570d38efe23a124e885f2f3e643a9206 (diff) | |
| parent | 6ebdc661b608671e9ca572af8bb42d58108cc008 (diff) | |
| download | op-kernel-dev-874f2f997dbe041a6c6e509dae8656ed9022d65d.zip op-kernel-dev-874f2f997dbe041a6c6e509dae8656ed9022d65d.tar.gz | |
Merge commit 'origin/master' into next
Manual merge of:
drivers/char/hvc_console.c
drivers/char/hvc_console.h
Diffstat (limited to 'arch/powerpc/platforms/85xx')
| -rw-r--r-- | arch/powerpc/platforms/85xx/mpc85xx_mds.c | 3 | ||||
| -rw-r--r-- | arch/powerpc/platforms/85xx/xes_mpc85xx.c | 4 |
2 files changed, 4 insertions, 3 deletions
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c index 04af81e..04d105d 100644 --- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c +++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c @@ -341,7 +341,8 @@ static void __init mpc85xx_mds_pic_init(void) } mpic = mpic_alloc(np, r.start, - MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN, + MPIC_PRIMARY | MPIC_WANTS_RESET | MPIC_BIG_ENDIAN | + MPIC_BROKEN_FRR_NIRQS, 0, 256, " OpenPIC "); BUG_ON(mpic == NULL); of_node_put(np); diff --git a/arch/powerpc/platforms/85xx/xes_mpc85xx.c b/arch/powerpc/platforms/85xx/xes_mpc85xx.c index 1b42605..0125604 100644 --- a/arch/powerpc/platforms/85xx/xes_mpc85xx.c +++ b/arch/powerpc/platforms/85xx/xes_mpc85xx.c @@ -80,8 +80,8 @@ static void xes_mpc85xx_configure_l2(void __iomem *l2_base) printk(KERN_INFO "xes_mpc85xx: Enabling L2 as cache\n"); ctl = MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2I; - if (machine_is_compatible("MPC8540") || - machine_is_compatible("MPC8560")) + if (of_machine_is_compatible("MPC8540") || + of_machine_is_compatible("MPC8560")) /* * Assume L2 SRAM is used fully for cache, so set * L2BLKSZ (bits 4:5) to match L2SIZ (bits 2:3). |
