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author | Christophe Leroy <christophe.leroy@c-s.fr> | 2016-02-09 17:08:21 +0100 |
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committer | Scott Wood <oss@buserror.net> | 2016-03-11 17:20:11 -0600 |
commit | 766d45cbeecc383b8ee230370b316d0b1e30d915 (patch) | |
tree | 934a848219ee9f1aea3291bd0fafbf4166fc7dee /arch/powerpc/mm | |
parent | a7761fe48993f103d6deac6037bf786bd1db0501 (diff) | |
download | op-kernel-dev-766d45cbeecc383b8ee230370b316d0b1e30d915.zip op-kernel-dev-766d45cbeecc383b8ee230370b316d0b1e30d915.tar.gz |
powerpc/8xx: rewrite flush_instruction_cache() in C
On PPC8xx, flushing instruction cache is performed by writing
in register SPRN_IC_CST. This registers suffers CPU6 ERRATA.
The patch rewrites the fonction in C so that CPU6 ERRATA will
be handled transparently
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Scott Wood <oss@buserror.net>
Diffstat (limited to 'arch/powerpc/mm')
-rw-r--r-- | arch/powerpc/mm/8xx_mmu.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/mm/8xx_mmu.c b/arch/powerpc/mm/8xx_mmu.c index 606d231..9491005 100644 --- a/arch/powerpc/mm/8xx_mmu.c +++ b/arch/powerpc/mm/8xx_mmu.c @@ -132,3 +132,10 @@ void set_context(unsigned long id, pgd_t *pgd) /* sync */ mb(); } + +void flush_instruction_cache(void) +{ + isync(); + mtspr(SPRN_IC_CST, IDC_INVALL); + isync(); +} |