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| author | Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> | 2016-11-24 15:09:54 +0530 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2016-11-25 14:18:25 +1100 |
| commit | 984d7a1ec67ce3a46324fa4bcb4c745bbc266cf2 (patch) | |
| tree | b195670447b52622a4f3b9679db3e6ec189d4054 /arch/powerpc/mm | |
| parent | a1ff57416af9a7971a801d553cd53edd8afb28d6 (diff) | |
| download | op-kernel-dev-984d7a1ec67ce3a46324fa4bcb4c745bbc266cf2.zip op-kernel-dev-984d7a1ec67ce3a46324fa4bcb4c745bbc266cf2.tar.gz | |
powerpc/mm: Fixup kernel read only mapping
With commit e58e87adc8bf9 ("powerpc/mm: Update _PAGE_KERNEL_RO") we
started using the ppp value 0b110 to map kernel readonly. But that
facility was only added as part of ISA 2.04. For earlier ISA version
only supported ppp bit value for readonly mapping is 0b011. (This
implies both user and kernel get mapped using the same ppp bit value for
readonly mapping.).
Update the code such that for earlier architecture version we use ppp
value 0b011 for readonly mapping. We don't differentiate between power5+
and power5 here and apply the new ppp bits only from power6 (ISA 2.05).
This keep the changes minimal.
This fixes issue with PS3 spu usage reported at
https://lkml.kernel.org/r/rep.1421449714.geoff@infradead.org
Fixes: e58e87adc8bf9 ("powerpc/mm: Update _PAGE_KERNEL_RO")
Cc: stable@vger.kernel.org # v4.7+
Tested-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/hash_utils_64.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/powerpc/mm/hash_utils_64.c b/arch/powerpc/mm/hash_utils_64.c index 5503078..78dabf06 100644 --- a/arch/powerpc/mm/hash_utils_64.c +++ b/arch/powerpc/mm/hash_utils_64.c @@ -193,8 +193,12 @@ unsigned long htab_convert_pte_flags(unsigned long pteflags) /* * Kernel read only mapped with ppp bits 0b110 */ - if (!(pteflags & _PAGE_WRITE)) - rflags |= (HPTE_R_PP0 | 0x2); + if (!(pteflags & _PAGE_WRITE)) { + if (mmu_has_feature(MMU_FTR_KERNEL_RO)) + rflags |= (HPTE_R_PP0 | 0x2); + else + rflags |= 0x3; + } } else { if (pteflags & _PAGE_RWX) rflags |= 0x2; |
