summaryrefslogtreecommitdiffstats
path: root/arch/powerpc/mm/tlb_nohash_low.S
diff options
context:
space:
mode:
authorKumar Gala <galak@kernel.crashing.org>2009-04-23 08:51:22 -0500
committerKumar Gala <galak@kernel.crashing.org>2009-04-23 08:51:22 -0500
commit323d23aeac4918c7a540b597a26fa7a67645593a (patch)
tree6d8861e65b1753168552f8e4b22a1f82d4ad7a41 /arch/powerpc/mm/tlb_nohash_low.S
parent6329db8bd60fbc0832f30c350b0181b8d865573e (diff)
downloadop-kernel-dev-323d23aeac4918c7a540b597a26fa7a67645593a.zip
op-kernel-dev-323d23aeac4918c7a540b597a26fa7a67645593a.tar.gz
Revert "powerpc: Add support for early tlbilx opcode"
This reverts commit e9965577406a2148ade97b5e0ce7c448b4ba4ef6. Our HW guys were able to fix this so it never sees the light of day. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/mm/tlb_nohash_low.S')
-rw-r--r--arch/powerpc/mm/tlb_nohash_low.S14
1 files changed, 1 insertions, 13 deletions
diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S
index 45fed36..788b87c 100644
--- a/arch/powerpc/mm/tlb_nohash_low.S
+++ b/arch/powerpc/mm/tlb_nohash_low.S
@@ -138,11 +138,7 @@ BEGIN_MMU_FTR_SECTION
andi. r3,r3,MMUCSR0_TLBFI@l
bne 1b
MMU_FTR_SECTION_ELSE
- BEGIN_MMU_FTR_SECTION_NESTED(96)
- PPC_TLBILX_ALL(0,r3)
- MMU_FTR_SECTION_ELSE_NESTED(96)
- PPC_TLBILX_ALL_EARLY(0,r3)
- ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
+ PPC_TLBILX_ALL(0,0)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
@@ -155,11 +151,7 @@ BEGIN_MMU_FTR_SECTION
wrteei 0
mfspr r4,SPRN_MAS6 /* save MAS6 */
mtspr SPRN_MAS6,r3
- BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_PID(0,0)
- MMU_FTR_SECTION_ELSE_NESTED(96)
- PPC_TLBILX_PID_EARLY(0,0)
- ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
mtspr SPRN_MAS6,r4 /* restore MAS6 */
wrtee r10
MMU_FTR_SECTION_ELSE
@@ -193,11 +185,7 @@ BEGIN_MMU_FTR_SECTION
mtspr SPRN_MAS1,r4
tlbwe
MMU_FTR_SECTION_ELSE
- BEGIN_MMU_FTR_SECTION_NESTED(96)
PPC_TLBILX_VA(0,r3)
- MMU_FTR_SECTION_ELSE_NESTED(96)
- PPC_TLBILX_VA_EARLY(0,r3)
- ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96)
ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX)
msync
isync
OpenPOWER on IntegriCloud