diff options
author | Alexander Graf <agraf@suse.de> | 2012-02-16 14:53:04 +0000 |
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committer | Avi Kivity <avi@redhat.com> | 2012-04-08 12:55:14 +0300 |
commit | e9ba39c1f3dff93efddacbd4569ada05633e2a9b (patch) | |
tree | 06006536ab6f4da04a82e47b593dc20bad8a291d /arch/powerpc/kvm/bookehv_interrupts.S | |
parent | 8a3da55784cf2aea8ef6acdd1f50e5ad52f76574 (diff) | |
download | op-kernel-dev-e9ba39c1f3dff93efddacbd4569ada05633e2a9b.zip op-kernel-dev-e9ba39c1f3dff93efddacbd4569ada05633e2a9b.tar.gz |
KVM: PPC: bookehv: disable MAS register updates early
We need to make sure that no MAS updates happen automatically while we
have the guest MAS registers loaded. So move the disabling code a bit
higher up so that it covers the full time we have guest values in MAS
registers.
The race this patch fixes should never occur, but it makes the code a
bit more logical to do it this way around.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Avi Kivity <avi@redhat.com>
Diffstat (limited to 'arch/powerpc/kvm/bookehv_interrupts.S')
-rw-r--r-- | arch/powerpc/kvm/bookehv_interrupts.S | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/powerpc/kvm/bookehv_interrupts.S b/arch/powerpc/kvm/bookehv_interrupts.S index dfa606d..3a1db90 100644 --- a/arch/powerpc/kvm/bookehv_interrupts.S +++ b/arch/powerpc/kvm/bookehv_interrupts.S @@ -358,6 +358,7 @@ _GLOBAL(kvmppc_resume_host) mtspr SPRN_MAS4, r6 stw r5, VCPU_SHARED_MAS7_3+0(r11) mtspr SPRN_MAS6, r8 + /* Enable MAS register updates via exception */ mfspr r3, SPRN_EPCR rlwinm r3, r3, 0, ~SPRN_EPCR_DMIUH mtspr SPRN_EPCR, r3 @@ -515,6 +516,11 @@ lightweight_exit: mtspr SPRN_PID, r3 PPC_LL r11, VCPU_SHARED(r4) + /* Disable MAS register updates via exception */ + mfspr r3, SPRN_EPCR + oris r3, r3, SPRN_EPCR_DMIUH@h + mtspr SPRN_EPCR, r3 + isync /* Save host mas4 and mas6 and load guest MAS registers */ mfspr r3, SPRN_MAS4 stw r3, VCPU_HOST_MAS4(r4) @@ -538,10 +544,6 @@ lightweight_exit: lwz r5, VCPU_SHARED_MAS7_3+0(r11) mtspr SPRN_MAS6, r3 mtspr SPRN_MAS7, r5 - /* Disable MAS register updates via exception */ - mfspr r3, SPRN_EPCR - oris r3, r3, SPRN_EPCR_DMIUH@h - mtspr SPRN_EPCR, r3 /* * Host interrupt handlers may have clobbered these guest-readable |