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authorKumar Gala <galak@kernel.crashing.org>2009-01-08 08:31:20 -0600
committerKumar Gala <galak@kernel.crashing.org>2009-01-28 18:16:50 -0600
commit105c31df6fc5a424b480321763b5598cf3817821 (patch)
treeda2bee2ae3db6b0af900947f60cb0c7bf1b9bd1f /arch/powerpc/kernel/head_booke.h
parent0585a155a7318e69d43ef20636c2f072ad17d03f (diff)
downloadop-kernel-dev-105c31df6fc5a424b480321763b5598cf3817821.zip
op-kernel-dev-105c31df6fc5a424b480321763b5598cf3817821.tar.gz
powerpc/fsl-booke: Cleanup init/exception setup to be runtime
We currently have a few variants of fsl-booke processors (e500v1, e500v2, e500mc, and e200). They all have minor differences that we had previously been handling via ifdefs. To move towards having this support the following changes have been made: * PID1, PID2 only exist on e500v1 & e500v2 and should not be accessed on e500mc or e200. We use MMUCFG[NPIDS] to determine which case we are since we only touch PID1/2 in extremely early init code. * Not all IVORs exist on all the processors so introduce cpu_setup functions for each variant to setup the proper IVORs that are either unique or exist but have some variations between the processors Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/kernel/head_booke.h')
-rw-r--r--arch/powerpc/kernel/head_booke.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/powerpc/kernel/head_booke.h b/arch/powerpc/kernel/head_booke.h
index fce2df9..bec1807 100644
--- a/arch/powerpc/kernel/head_booke.h
+++ b/arch/powerpc/kernel/head_booke.h
@@ -70,10 +70,10 @@
/* only on e500mc/e200 */
#define DEBUG_STACK_BASE dbgirq_ctx
-#ifdef CONFIG_PPC_E500MC
-#define DEBUG_SPRG SPRN_SPRG9
-#else
+#ifdef CONFIG_E200
#define DEBUG_SPRG SPRN_SPRG6W
+#else
+#define DEBUG_SPRG SPRN_SPRG9
#endif
#define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
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