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| author | Andy Fleming <afleming@freescale.com> | 2011-12-08 01:20:27 -0600 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2014-07-29 19:26:20 -0500 |
| commit | e16c8765533a155ebd3d7c36fc80440a03bbf46a (patch) | |
| tree | 8e4c3ab9fd85d3a852889c13012017b5cf8770b7 /arch/powerpc/kernel/head_64.S | |
| parent | 7251a24e4d3acf2d7826e1c42fe84258c312a742 (diff) | |
| download | op-kernel-dev-e16c8765533a155ebd3d7c36fc80440a03bbf46a.zip op-kernel-dev-e16c8765533a155ebd3d7c36fc80440a03bbf46a.tar.gz | |
powerpc/e6500: Add support for hardware threads
The general idea is that each core will release all of its
threads into the secondary thread startup code, which will
eventually wait in the secondary core holding area, for the
appropriate bit in the PACA to be set. The kick_cpu function
pointer will set that bit in the PACA, and thus "release"
the core/thread to boot. We also need to do a few things that
U-Boot normally does for CPUs (like enable branch prediction).
Signed-off-by: Andy Fleming <afleming@freescale.com>
[scottwood@freescale.com: various changes, including only enabling
threads if Linux wants to kick them]
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'arch/powerpc/kernel/head_64.S')
| -rw-r--r-- | arch/powerpc/kernel/head_64.S | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/head_64.S b/arch/powerpc/kernel/head_64.S index a95145d..36ff6f03 100644 --- a/arch/powerpc/kernel/head_64.S +++ b/arch/powerpc/kernel/head_64.S @@ -180,6 +180,28 @@ exception_marker: #include "exceptions-64s.S" #endif +#ifdef CONFIG_PPC_BOOK3E +_GLOBAL(fsl_secondary_thread_init) + /* Enable branch prediction */ + lis r3,BUCSR_INIT@h + ori r3,r3,BUCSR_INIT@l + mtspr SPRN_BUCSR,r3 + isync + + /* + * Fix PIR to match the linear numbering in the device tree. + * + * On e6500, the reset value of PIR uses the low three bits for + * the thread within a core, and the upper bits for the core + * number. There are two threads per core, so shift everything + * but the low bit right by two bits so that the cpu numbering is + * continuous. + */ + mfspr r3, SPRN_PIR + rlwimi r3, r3, 30, 2, 30 + mtspr SPRN_PIR, r3 +#endif + _GLOBAL(generic_secondary_thread_init) mr r24,r3 |
