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| author | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-09-04 04:08:20 +0000 |
|---|---|---|
| committer | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-09-30 09:23:15 -0400 |
| commit | fbcc4bacee30cad4e4a13d05492a9ed0c9c3e8c7 (patch) | |
| tree | 04e9f7baf7db1c2f1b7d49af72e353a5ecc1e2f4 /arch/powerpc/include/asm | |
| parent | ec4f9945b5b3e9e491a04eb1efe1c959371fa6de (diff) | |
| download | op-kernel-dev-fbcc4bacee30cad4e4a13d05492a9ed0c9c3e8c7.zip op-kernel-dev-fbcc4bacee30cad4e4a13d05492a9ed0c9c3e8c7.tar.gz | |
ibm_newemac: MAL support for PowerPC 405EZ
The PowerPC 405EZ SoC has some differences in the interrupt layout and
handling for the MAL. The SERR, TXDE, and RXDE interrupts are OR'd into
a single interrupt. Also, due to the possibility for interrupt coalescing,
the TXEOB and RXEOB interrupts require an interrupt bit to be cleared in
the ICINTSTAT SDR.
This sets the proper MAL feature bits for 405EZ boards, and adds a common
shared handler for SERR, TXDE, and RXDE. The defines for the ICINTSTAT DCR
are added to the proper header file as well.
This has been adapted from code originally written by Stefan Roese.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Jeff Garzik <jeff@garzik.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Diffstat (limited to 'arch/powerpc/include/asm')
| -rw-r--r-- | arch/powerpc/include/asm/dcr-regs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/dcr-regs.h b/arch/powerpc/include/asm/dcr-regs.h index 29b0ece..7b833ff 100644 --- a/arch/powerpc/include/asm/dcr-regs.h +++ b/arch/powerpc/include/asm/dcr-regs.h @@ -68,6 +68,13 @@ #define SDR0_UART3 0x0123 #define SDR0_CUST0 0x4000 +/* SDR for 405EZ */ +#define DCRN_SDR_ICINTSTAT 0x4510 +#define ICINTSTAT_ICRX 0x80000000 +#define ICINTSTAT_ICTX0 0x40000000 +#define ICINTSTAT_ICTX1 0x20000000 +#define ICINTSTAT_ICTX 0x60000000 + /* * All those DCR register addresses are offsets from the base address * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is |
