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author | Ingo Molnar <mingo@elte.hu> | 2008-08-14 14:58:01 +0200 |
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committer | Ingo Molnar <mingo@elte.hu> | 2008-08-14 14:58:01 +0200 |
commit | 51ca3c679194e7435c25b8e77b0a73c597e41ae9 (patch) | |
tree | a681dca369607ab0f371d5246b0f75140b860a8a /arch/powerpc/include/asm/reg_8xx.h | |
parent | b55793f7528ce1b73c25b3ac8a86a6cda2a0f9a4 (diff) | |
parent | b635acec48bcaa9183fcbf4e3955616b0d4119b5 (diff) | |
download | op-kernel-dev-51ca3c679194e7435c25b8e77b0a73c597e41ae9.zip op-kernel-dev-51ca3c679194e7435c25b8e77b0a73c597e41ae9.tar.gz |
Merge branch 'linus' into x86/core
Conflicts:
arch/x86/kernel/genapic_64.c
include/asm-x86/kvm_host.h
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/include/asm/reg_8xx.h')
-rw-r--r-- | arch/powerpc/include/asm/reg_8xx.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h new file mode 100644 index 0000000..e8ea346 --- /dev/null +++ b/arch/powerpc/include/asm/reg_8xx.h @@ -0,0 +1,42 @@ +/* + * Contains register definitions common to PowerPC 8xx CPUs. Notice + */ +#ifndef _ASM_POWERPC_REG_8xx_H +#define _ASM_POWERPC_REG_8xx_H + +/* Cache control on the MPC8xx is provided through some additional + * special purpose registers. + */ +#define SPRN_IC_CST 560 /* Instruction cache control/status */ +#define SPRN_IC_ADR 561 /* Address needed for some commands */ +#define SPRN_IC_DAT 562 /* Read-only data register */ +#define SPRN_DC_CST 568 /* Data cache control/status */ +#define SPRN_DC_ADR 569 /* Address needed for some commands */ +#define SPRN_DC_DAT 570 /* Read-only data register */ + +/* Commands. Only the first few are available to the instruction cache. +*/ +#define IDC_ENABLE 0x02000000 /* Cache enable */ +#define IDC_DISABLE 0x04000000 /* Cache disable */ +#define IDC_LDLCK 0x06000000 /* Load and lock */ +#define IDC_UNLINE 0x08000000 /* Unlock line */ +#define IDC_UNALL 0x0a000000 /* Unlock all */ +#define IDC_INVALL 0x0c000000 /* Invalidate all */ + +#define DC_FLINE 0x0e000000 /* Flush data cache line */ +#define DC_SFWT 0x01000000 /* Set forced writethrough mode */ +#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */ +#define DC_SLES 0x05000000 /* Set little endian swap mode */ +#define DC_CLES 0x07000000 /* Clear little endian swap mode */ + +/* Status. +*/ +#define IDC_ENABLED 0x80000000 /* Cache is enabled */ +#define IDC_CERR1 0x00200000 /* Cache error 1 */ +#define IDC_CERR2 0x00100000 /* Cache error 2 */ +#define IDC_CERR3 0x00080000 /* Cache error 3 */ + +#define DC_DFWT 0x40000000 /* Data cache is forced write through */ +#define DC_LES 0x20000000 /* Caches are little endian mode */ + +#endif /* _ASM_POWERPC_REG_8xx_H */ |