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authorAlistair Popple <alistair@popple.id.au>2015-12-17 13:43:13 +1100
committerMichael Ellerman <mpe@ellerman.id.au>2015-12-17 22:41:00 +1100
commit5d2aa710e697244f5504125e4aa6e2cfcf6c4791 (patch)
tree92d41bd995ab538e0de8b57c0de8b66cea204cc0 /arch/powerpc/include/asm/pci.h
parenta84bf321401ab206baafbbfd3bfad485a1a2c3b4 (diff)
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op-kernel-dev-5d2aa710e697244f5504125e4aa6e2cfcf6c4791.tar.gz
powerpc/powernv: Add support for Nvlink NPUs
NVLink is a high speed interconnect that is used in conjunction with a PCI-E connection to create an interface between CPU and GPU that provides very high data bandwidth. A PCI-E connection to a GPU is used as the control path to initiate and report status of large data transfers sent via the NVLink. On IBM Power systems the NVLink processing unit (NPU) is similar to the existing PHB3. This patch adds support for a new NPU PHB type. DMA operations on the NPU are not supported as this patch sets the TCE translation tables to be the same as the related GPU PCIe device for each NVLink. Therefore all DMA operations are setup and controlled via the PCIe device. EEH is not presently supported for the NPU devices, although it may be added in future. Signed-off-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/pci.h')
-rw-r--r--arch/powerpc/include/asm/pci.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/pci.h b/arch/powerpc/include/asm/pci.h
index 3453bd8..6f8065a 100644
--- a/arch/powerpc/include/asm/pci.h
+++ b/arch/powerpc/include/asm/pci.h
@@ -149,4 +149,8 @@ extern void pcibios_setup_phb_io_space(struct pci_controller *hose);
extern void pcibios_scan_phb(struct pci_controller *hose);
#endif /* __KERNEL__ */
+
+extern struct pci_dev *pnv_pci_get_gpu_dev(struct pci_dev *npdev);
+extern struct pci_dev *pnv_pci_get_npu_dev(struct pci_dev *gpdev, int index);
+
#endif /* __ASM_POWERPC_PCI_H */
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