diff options
| author | Ingo Molnar <mingo@elte.hu> | 2009-04-08 10:35:30 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-04-08 10:35:30 +0200 |
| commit | 5ea472a77f8e4811ceee3f44a9deda6ad6e8b789 (patch) | |
| tree | a9ec5019e2b666a19874fc344ffb0dd5da6bce94 /arch/powerpc/include/asm/mpic.h | |
| parent | 6c009ecef8cca28c7c09eb16d0802e37915a76e1 (diff) | |
| parent | 577c9c456f0e1371cbade38eaf91ae8e8a308555 (diff) | |
| download | op-kernel-dev-5ea472a77f8e4811ceee3f44a9deda6ad6e8b789.zip op-kernel-dev-5ea472a77f8e4811ceee3f44a9deda6ad6e8b789.tar.gz | |
Merge commit 'v2.6.30-rc1' into perfcounters/core
Conflicts:
arch/powerpc/include/asm/systbl.h
arch/powerpc/include/asm/unistd.h
include/linux/init_task.h
Merge reason: the conflicts are non-trivial: PowerPC placement
of sys_perf_counter_open has to be mixed with the
new preadv/pwrite syscalls.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/powerpc/include/asm/mpic.h')
| -rw-r--r-- | arch/powerpc/include/asm/mpic.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/mpic.h b/arch/powerpc/include/asm/mpic.h index c2ccca5..a002682 100644 --- a/arch/powerpc/include/asm/mpic.h +++ b/arch/powerpc/include/asm/mpic.h @@ -22,6 +22,14 @@ #define MPIC_GREG_FEATURE_1 0x00010 #define MPIC_GREG_GLOBAL_CONF_0 0x00020 #define MPIC_GREG_GCONF_RESET 0x80000000 +/* On the FSL mpic implementations the Mode field is expand to be + * 2 bits wide: + * 0b00 = pass through (interrupts routed to IRQ0) + * 0b01 = Mixed mode + * 0b10 = reserved + * 0b11 = External proxy / coreint + */ +#define MPIC_GREG_GCONF_COREINT 0x60000000 #define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000 #define MPIC_GREG_GCONF_NO_BIAS 0x10000000 #define MPIC_GREG_GCONF_BASE_MASK 0x000fffff @@ -357,6 +365,8 @@ struct mpic #define MPIC_BROKEN_FRR_NIRQS 0x00000800 /* Destination only supports a single CPU at a time */ #define MPIC_SINGLE_DEST_CPU 0x00001000 +/* Enable CoreInt delivery of interrupts */ +#define MPIC_ENABLE_COREINT 0x00002000 /* MPIC HW modification ID */ #define MPIC_REGSET_MASK 0xf0000000 @@ -470,6 +480,8 @@ extern void mpic_end_irq(unsigned int irq); extern unsigned int mpic_get_one_irq(struct mpic *mpic); /* This one gets from the primary mpic */ extern unsigned int mpic_get_irq(void); +/* This one gets from the primary mpic via CoreInt*/ +extern unsigned int mpic_get_coreint_irq(void); /* Fetch Machine Check interrupt from primary mpic */ extern unsigned int mpic_get_mcirq(void); |
