diff options
author | Boqun Feng <boqun.feng@gmail.com> | 2015-11-02 09:30:31 +0800 |
---|---|---|
committer | Michael Ellerman <mpe@ellerman.id.au> | 2015-12-14 20:38:18 +1100 |
commit | 49e9cf3f0c04bf76ffa59242254110309554861d (patch) | |
tree | a8dad7893126a02ebb18c88ea0d374502cf68beb /arch/powerpc/include/asm/cmpxchg.h | |
parent | 4dcbd88eb600d52ce52a75c5075c2eff2f6849e6 (diff) | |
download | op-kernel-dev-49e9cf3f0c04bf76ffa59242254110309554861d.zip op-kernel-dev-49e9cf3f0c04bf76ffa59242254110309554861d.tar.gz |
powerpc: Make value-returning atomics fully ordered
According to memory-barriers.txt:
> Any atomic operation that modifies some state in memory and returns
> information about the state (old or new) implies an SMP-conditional
> general memory barrier (smp_mb()) on each side of the actual
> operation ...
Which mean these operations should be fully ordered. However on PPC,
PPC_ATOMIC_ENTRY_BARRIER is the barrier before the actual operation,
which is currently "lwsync" if SMP=y. The leading "lwsync" can not
guarantee fully ordered atomics, according to Paul Mckenney:
https://lkml.org/lkml/2015/10/14/970
To fix this, we define PPC_ATOMIC_ENTRY_BARRIER as "sync" to guarantee
the fully-ordered semantics.
This also makes futex atomics fully ordered, which can avoid possible
memory ordering problems if userspace code relies on futex system call
for fully ordered semantics.
Fixes: b97021f85517 ("powerpc: Fix atomic_xxx_return barrier semantics")
Cc: stable@vger.kernel.org # 3.2+
Signed-off-by: Boqun Feng <boqun.feng@gmail.com>
Reviewed-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Acked-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/cmpxchg.h')
0 files changed, 0 insertions, 0 deletions