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authorGrant Grundler <grundler@parisc-linux.org>2005-11-17 16:29:16 -0500
committerKyle McMartin <kyle@parisc-linux.org>2005-11-17 16:29:16 -0500
commit03afe22f074231196dcf3298f962cfc787ebbc60 (patch)
tree9a1b4400f387f46dd2009500dc1d4f2fa0a15f44 /arch/parisc
parentc2ab64d09815cc4d48347ee3679658f197455a2a (diff)
downloadop-kernel-dev-03afe22f074231196dcf3298f962cfc787ebbc60.zip
op-kernel-dev-03afe22f074231196dcf3298f962cfc787ebbc60.tar.gz
[PARISC] irq_affinityp[] only available for SMP builds
irq_affinityp[] only available for SMP builds, make code that uses it conditional on CONFIG_SMP. Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
Diffstat (limited to 'arch/parisc')
-rw-r--r--arch/parisc/kernel/irq.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/arch/parisc/kernel/irq.c b/arch/parisc/kernel/irq.c
index 2626405..144fc25 100644
--- a/arch/parisc/kernel/irq.c
+++ b/arch/parisc/kernel/irq.c
@@ -261,13 +261,17 @@ int txn_alloc_irq(unsigned int bits_wide)
return -1;
}
+
unsigned long txn_affinity_addr(unsigned int irq, int cpu)
{
+#ifdef CONFIG_SMP
irq_affinity[irq] = cpumask_of_cpu(cpu);
+#endif
return cpu_data[cpu].txn_addr;
}
+
unsigned long txn_alloc_addr(unsigned int virt_irq)
{
static int next_cpu = -1;
@@ -321,14 +325,16 @@ void do_cpu_irq_mask(struct pt_regs *regs)
/* Work our way from MSb to LSb...same order we alloc EIRs */
for (irq = TIMER_IRQ; eirr_val && bit; bit>>=1, irq++) {
+#ifdef CONFIG_SMP
cpumask_t dest = irq_affinity[irq];
-
+#endif
if (!(bit & eirr_val))
continue;
/* clear bit in mask - can exit loop sooner */
eirr_val &= ~bit;
+#ifdef CONFIG_SMP
/* FIXME: because generic set affinity mucks
* with the affinity before sending it to us
* we can get the situation where the affinity is
@@ -337,12 +343,13 @@ void do_cpu_irq_mask(struct pt_regs *regs)
!cpu_isset(smp_processor_id(), dest)) {
int cpu = first_cpu(dest);
- printk("rethrowing irq %d from %d to %d\n",
+ printk("redirecting irq %d from CPU %d to %d\n",
irq, smp_processor_id(), cpu);
gsc_writel(irq + CPU_IRQ_BASE,
cpu_data[cpu].hpa);
continue;
}
+#endif
__do_IRQ(irq, regs);
}
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