summaryrefslogtreecommitdiffstats
path: root/arch/parisc/mm/fault.c
diff options
context:
space:
mode:
authorHelge Deller <deller@gmx.de>2013-11-18 22:12:11 +0100
committerHelge Deller <deller@gmx.de>2013-11-19 23:36:18 +0100
commit49d1cb2bcadfc5cea4b700a0ec6b957567889714 (patch)
tree233750543d819d8a12fefdc0b244b883c2c4e5b3 /arch/parisc/mm/fault.c
parent38c7937379276a5ea8c54481205003af2f2b5694 (diff)
downloadop-kernel-dev-49d1cb2bcadfc5cea4b700a0ec6b957567889714.zip
op-kernel-dev-49d1cb2bcadfc5cea4b700a0ec6b957567889714.tar.gz
parisc: improve SIGBUS/SIGSEGV error reporting
This patch fixes most of the Linux Test Project testcases, e.g. fstat05. Signed-off-by: Helge Deller <deller@gmx.de>
Diffstat (limited to 'arch/parisc/mm/fault.c')
-rw-r--r--arch/parisc/mm/fault.c22
1 files changed, 20 insertions, 2 deletions
diff --git a/arch/parisc/mm/fault.c b/arch/parisc/mm/fault.c
index 7584a5d..9d08c71 100644
--- a/arch/parisc/mm/fault.c
+++ b/arch/parisc/mm/fault.c
@@ -282,16 +282,34 @@ bad_area:
#endif
switch (code) {
case 15: /* Data TLB miss fault/Data page fault */
+ /* send SIGSEGV when outside of vma */
+ if (!vma ||
+ address < vma->vm_start || address > vma->vm_end) {
+ si.si_signo = SIGSEGV;
+ si.si_code = SEGV_MAPERR;
+ break;
+ }
+
+ /* send SIGSEGV for wrong permissions */
+ if ((vma->vm_flags & acc_type) != acc_type) {
+ si.si_signo = SIGSEGV;
+ si.si_code = SEGV_ACCERR;
+ break;
+ }
+
+ /* probably address is outside of mapped file */
+ /* fall through */
case 17: /* NA data TLB miss / page fault */
case 18: /* Unaligned access - PCXS only */
si.si_signo = SIGBUS;
- si.si_code = BUS_ADRERR;
+ si.si_code = (code == 18) ? BUS_ADRALN : BUS_ADRERR;
break;
case 16: /* Non-access instruction TLB miss fault */
case 26: /* PCXL: Data memory access rights trap */
default:
si.si_signo = SIGSEGV;
- si.si_code = SEGV_MAPERR;
+ si.si_code = (code == 26) ? SEGV_ACCERR : SEGV_MAPERR;
+ break;
}
si.si_errno = 0;
si.si_addr = (void __user *) address;
OpenPOWER on IntegriCloud