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authorMark Brown <broonie@kernel.org>2015-01-07 17:30:17 +0000
committerMark Brown <broonie@kernel.org>2015-01-07 17:30:17 +0000
commit1285c3fefaddedf5358f52cfde3c2b64d8086a04 (patch)
tree361f556d6b400e8cb6d16738142db2f69f63ef2f /arch/parisc/include/asm/ldcw.h
parent6b038c8d2b99b552f0b025c8a134f8a3c417a3e7 (diff)
parentb1940cd21c0f4abdce101253e860feff547291b0 (diff)
downloadop-kernel-dev-1285c3fefaddedf5358f52cfde3c2b64d8086a04.zip
op-kernel-dev-1285c3fefaddedf5358f52cfde3c2b64d8086a04.tar.gz
Merge tag 'v3.19-rc3' into spi-sh-msiof
Linux 3.19-rc3
Diffstat (limited to 'arch/parisc/include/asm/ldcw.h')
-rw-r--r--arch/parisc/include/asm/ldcw.h13
1 files changed, 10 insertions, 3 deletions
diff --git a/arch/parisc/include/asm/ldcw.h b/arch/parisc/include/asm/ldcw.h
index d2d11b7..8121aa6 100644
--- a/arch/parisc/include/asm/ldcw.h
+++ b/arch/parisc/include/asm/ldcw.h
@@ -33,11 +33,18 @@
#endif /*!CONFIG_PA20*/
-/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*. */
+/* LDCW, the only atomic read-write operation PA-RISC has. *sigh*.
+ We don't explicitly expose that "*a" may be written as reload
+ fails to find a register in class R1_REGS when "a" needs to be
+ reloaded when generating 64-bit PIC code. Instead, we clobber
+ memory to indicate to the compiler that the assembly code reads
+ or writes to items other than those listed in the input and output
+ operands. This may pessimize the code somewhat but __ldcw is
+ usually used within code blocks surrounded by memory barriors. */
#define __ldcw(a) ({ \
unsigned __ret; \
- __asm__ __volatile__(__LDCW " 0(%2),%0" \
- : "=r" (__ret), "+m" (*(a)) : "r" (a)); \
+ __asm__ __volatile__(__LDCW " 0(%1),%0" \
+ : "=r" (__ret) : "r" (a) : "memory"); \
__ret; \
})
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