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| author | Jonas Bonn <jonas@southpole.se> | 2011-11-18 14:40:04 +0100 |
|---|---|---|
| committer | Jonas Bonn <jonas@southpole.se> | 2012-02-17 10:08:19 +0100 |
| commit | 754d5c2bf65847f7ff4e0047a830154abe666112 (patch) | |
| tree | 31fa395b798aa8e2d0f4cf9f5d4b8f116ad21dd1 /arch/openrisc | |
| parent | 17425275112960af0dc9882c06c343d3b6ec8dc9 (diff) | |
| download | op-kernel-dev-754d5c2bf65847f7ff4e0047a830154abe666112.zip op-kernel-dev-754d5c2bf65847f7ff4e0047a830154abe666112.tar.gz | |
openrisc: Set shortest clock event to 100 ticks
It takes a couple of instructions to actually configure a clock event
so setting an alarm just 1 clock cycle in the future isn't going to work;
doing so results in setting an alarm in the "past" in which case the event
won't fire until the timer overflows and rolls back around to the "current
time".
Not quite sure how many clock cycles it actually takes to get through to
actually writing the register, but 100 seems to work reliably.
Use generic helper to set up the clock event while we're at it.
Reported-by: Jan Schulte <jan.schulte@aacmicrotec.com>
Signed-off-by: Jonas Bonn <jonas@southpole.se>
Diffstat (limited to 'arch/openrisc')
| -rw-r--r-- | arch/openrisc/kernel/time.c | 13 |
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/openrisc/kernel/time.c b/arch/openrisc/kernel/time.c index bd946ef..7c52e94 100644 --- a/arch/openrisc/kernel/time.c +++ b/arch/openrisc/kernel/time.c @@ -125,16 +125,13 @@ irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs) static __init void openrisc_clockevent_init(void) { - clockevents_calc_mult_shift(&clockevent_openrisc_timer, - cpuinfo.clock_frequency, 4); + clockevent_openrisc_timer.cpumask = cpumask_of(0); /* We only have 28 bits */ - clockevent_openrisc_timer.max_delta_ns = - clockevent_delta2ns((u32) 0x0fffffff, &clockevent_openrisc_timer); - clockevent_openrisc_timer.min_delta_ns = - clockevent_delta2ns(1, &clockevent_openrisc_timer); - clockevent_openrisc_timer.cpumask = cpumask_of(0); - clockevents_register_device(&clockevent_openrisc_timer); + clockevents_config_and_register(&clockevent_openrisc_timer, + cpuinfo.clock_frequency, + 100, 0x0fffffff); + } /** |
