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| author | John Crispin <blogic@openwrt.org> | 2013-08-23 08:31:31 +0200 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2013-09-04 16:57:31 +0200 |
| commit | 68c9b7ed9ead9c5b38c2efa690b6bdae00a09d8c (patch) | |
| tree | 6a0ce7bee163bee9e7c3cf492eee5edb141b33f2 /arch/mips | |
| parent | ded1e9d727f0e7cb1cf7f243dac2a87974ae048f (diff) | |
| download | op-kernel-dev-68c9b7ed9ead9c5b38c2efa690b6bdae00a09d8c.zip op-kernel-dev-68c9b7ed9ead9c5b38c2efa690b6bdae00a09d8c.tar.gz | |
MIPS: ralink: mt7620: Add wdt clock definition
The watchdog driver of the SoC uses the clk API to
get the clock associated with the watchdog device.
However the MT7620 specific setup code does not
register a clock for the watchdog device yet which
leads to the following error:
rt2880_wdt: probe of 10000120.watchdog failed with error -2
Register a clock device for the watchdog in order to
avoid the error and make the watchdog usable.
Signed-off-by: John Crispin <blogic@openwrt.org>
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5756/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/ralink/mt7620.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c index 61dcee8..7759c5a 100644 --- a/arch/mips/ralink/mt7620.c +++ b/arch/mips/ralink/mt7620.c @@ -316,6 +316,7 @@ void __init ralink_clk_init(void) ralink_clk_add("cpu", cpu_rate); ralink_clk_add("10000100.timer", periph_rate); + ralink_clk_add("10000120.watchdog", periph_rate); ralink_clk_add("10000500.uart", periph_rate); ralink_clk_add("10000c00.uartlite", periph_rate); } |
