diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-10-31 22:49:04 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-11-01 17:46:09 +0000 |
| commit | cb56837ea5f15fa5279fd490f292134c3a92e5de (patch) | |
| tree | a6da64b1906b9459888687fc28f0bccdbe96ce42 /arch/mips | |
| parent | 242954b5aa8e5ec84f46a84637daf08ee4247c6e (diff) | |
| download | op-kernel-dev-cb56837ea5f15fa5279fd490f292134c3a92e5de.zip op-kernel-dev-cb56837ea5f15fa5279fd490f292134c3a92e5de.tar.gz | |
[MIPS] SMTC: Fix crash if # of TC's > # of VPE's after pt_regs irq cleanup.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/kernel/entry.S | 3 | ||||
| -rw-r--r-- | arch/mips/kernel/smtc-asm.S | 7 |
2 files changed, 9 insertions, 1 deletions
diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S index 417c08a..f10b6a1 100644 --- a/arch/mips/kernel/entry.S +++ b/arch/mips/kernel/entry.S @@ -83,7 +83,10 @@ FEXPORT(syscall_exit) FEXPORT(restore_all) # restore full frame #ifdef CONFIG_MIPS_MT_SMTC /* Detect and execute deferred IPI "interrupts" */ + LONG_L s0, TI_REGS($28) + LONG_S sp, TI_REGS($28) jal deferred_smtc_ipi + LONG_S s0, TI_REGS($28) /* Re-arm any temporarily masked interrupts not explicitly "acked" */ mfc0 v0, CP0_TCSTATUS ori v1, v0, TCSTATUS_IXMT diff --git a/arch/mips/kernel/smtc-asm.S b/arch/mips/kernel/smtc-asm.S index 1cb9441..921207c 100644 --- a/arch/mips/kernel/smtc-asm.S +++ b/arch/mips/kernel/smtc-asm.S @@ -101,7 +101,9 @@ FEXPORT(__smtc_ipi_vector) lw t0,PT_PADSLOT5(sp) /* Argument from sender passed in stack pad slot 4 */ lw a0,PT_PADSLOT4(sp) - PTR_LA ra, _ret_from_irq + LONG_L s0, TI_REGS($28) + LONG_S sp, TI_REGS($28) + PTR_LA ra, ret_from_irq jr t0 /* @@ -119,7 +121,10 @@ LEAF(self_ipi) subu t1,sp,PT_SIZE sw ra,PT_EPC(t1) sw a0,PT_PADSLOT4(t1) + LONG_L s0, TI_REGS($28) + LONG_S sp, TI_REGS($28) la t2,ipi_decode + LONG_S s0, TI_REGS($28) sw t2,PT_PADSLOT5(t1) /* Save pre-disable value of TCStatus */ sw t0,PT_TCSTATUS(t1) |
