diff options
| author | Ganesan Ramalingam <ganesanr@broadcom.com> | 2015-01-07 16:58:26 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-10 15:41:43 +0200 |
| commit | 872cd4c2c617bb3a203ebe18115fd0c697112b87 (patch) | |
| tree | bec428d78dd665f576b9fb213b1208ad998509c0 /arch/mips | |
| parent | b083518c52ab75a345d668ca7fa41e530df08d51 (diff) | |
| download | op-kernel-dev-872cd4c2c617bb3a203ebe18115fd0c697112b87.zip op-kernel-dev-872cd4c2c617bb3a203ebe18115fd0c697112b87.tar.gz | |
MIPS: Netlogic: Fix for SATA PHY init
Update to the SATA PHY initialization. This is needed for SATA detection
to succeed in all configurations.
Signed-off-by: Ganesan Ramalingam <ganesanr@broadcom.com>
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8886/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
| -rw-r--r-- | arch/mips/netlogic/xlp/ahci-init-xlp2.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/mips/netlogic/xlp/ahci-init-xlp2.c b/arch/mips/netlogic/xlp/ahci-init-xlp2.c index c83dbf3..7b066a4 100644 --- a/arch/mips/netlogic/xlp/ahci-init-xlp2.c +++ b/arch/mips/netlogic/xlp/ahci-init-xlp2.c @@ -203,6 +203,7 @@ static u8 read_phy_reg(u64 regbase, u32 addr, u32 physel) static void config_sata_phy(u64 regbase) { u32 port, i, reg; + u8 val; for (port = 0; port < 2; port++) { for (i = 0, reg = RXCDRCALFOSC0; reg <= CALDUTY; reg++, i++) @@ -210,6 +211,18 @@ static void config_sata_phy(u64 regbase) for (i = 0, reg = RXDPIF; reg <= PPMDRIFTMAX_HI; reg++, i++) write_phy_reg(regbase, reg, port, sata_phy_config2[i]); + + /* Fix for PHY link up failures at lower temperatures */ + write_phy_reg(regbase, 0x800F, port, 0x1f); + + val = read_phy_reg(regbase, 0x0029, port); + write_phy_reg(regbase, 0x0029, port, val | (0x7 << 1)); + + val = read_phy_reg(regbase, 0x0056, port); + write_phy_reg(regbase, 0x0056, port, val & ~(1 << 3)); + + val = read_phy_reg(regbase, 0x0018, port); + write_phy_reg(regbase, 0x0018, port, val & ~(0x7 << 0)); } } |
