diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2005-10-01 13:06:32 +0100 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:32:32 +0100 |
commit | 02cf2119684e52e97a8a90bd7630386e0f1a250a (patch) | |
tree | fbe051feacc403d7703bf27043ac048b5d2f2369 /arch/mips | |
parent | 942d042d17c77febab9af6815b2e77f665d0f9c1 (diff) | |
download | op-kernel-dev-02cf2119684e52e97a8a90bd7630386e0f1a250a.zip op-kernel-dev-02cf2119684e52e97a8a90bd7630386e0f1a250a.tar.gz |
Cleanup the mess in cpu_cache_init.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 25 | ||||
-rw-r--r-- | arch/mips/mm/c-r3k.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/c-r4k.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/c-sb1.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/c-tx39.c | 2 | ||||
-rw-r--r-- | arch/mips/mm/cache.c | 90 |
6 files changed, 62 insertions, 61 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5d71eca..8e6427a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -191,7 +191,7 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } -#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \ +#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) static inline void cpu_probe_legacy(struct cpuinfo_mips *c) @@ -200,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) case PRID_IMP_R2000: c->cputype = CPU_R2000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -214,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) else c->cputype = CPU_R3000; c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX; + c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | + MIPS_CPU_NOFPUEX; if (__cpu_has_fpu()) c->options |= MIPS_CPU_FPU; c->tlbsize = 64; @@ -297,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c) #endif case PRID_IMP_TX39: c->isa_level = MIPS_CPU_ISA_I; - c->options = MIPS_CPU_TLB; + c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { c->cputype = CPU_TX3927; @@ -441,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c) config0 = read_c0_config(); if (((config0 & MIPS_CONF_MT) >> 7) == 1) - c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB; + c->options |= MIPS_CPU_TLB; isa = (config0 & MIPS_CONF_AT) >> 13; switch (isa) { case 0: @@ -516,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) static inline void decode_configs(struct cpuinfo_mips *c) { /* MIPS32 or MIPS64 compliant CPU. */ - c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC | - MIPS_CPU_LLSC | MIPS_CPU_MCHECK; + c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | + MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; c->scache.flags = MIPS_CACHE_NOT_PRESENT; @@ -603,6 +605,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c) static inline void cpu_probe_sibyte(struct cpuinfo_mips *c) { decode_configs(c); + + /* + * For historical reasons the SB1 comes with it's own variant of + * cache code which eventually will be folded into c-r4k.c. Until + * then we pretend it's got it's own cache architecture. + */ + c->options &= MIPS_CPU_4K_CACHE; + c->options |= MIPS_CPU_SB1_CACHE; + switch (c->processor_id & 0xff00) { case PRID_IMP_SB1: c->cputype = CPU_SB1; diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 03492a5..27f4fa2 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -319,7 +319,7 @@ static void r3k_dma_cache_wback_inv(unsigned long start, unsigned long size) r3k_flush_dcache_range(start, start + size); } -void __init ld_mmu_r23000(void) +void __init r3k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index aa87ae5..31f080b 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1221,7 +1221,7 @@ static inline void coherency_setup(void) } } -void __init ld_mmu_r4xx0(void) +void __init r4k_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); diff --git a/arch/mips/mm/c-sb1.c b/arch/mips/mm/c-sb1.c index d183dbc..70d1ab3 100644 --- a/arch/mips/mm/c-sb1.c +++ b/arch/mips/mm/c-sb1.c @@ -496,7 +496,7 @@ static __init void probe_cache_sizes(void) * memory management function pointers, as well as initialize * the caches and tlbs */ -void ld_mmu_sb1(void) +void sb1_cache_init(void) { extern char except_vec2_sb1; extern char handle_vec2_sb1; diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index c3ba81d..0a97a94 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -410,7 +410,7 @@ static __init void tx39_probe_cache(void) } } -void __init ld_mmu_tx39(void) +void __init tx39_cache_init(void) { extern void build_clear_page(void); extern void build_copy_page(void); diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 172293b..611b48d 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -104,58 +104,48 @@ void __update_cache(struct vm_area_struct *vma, unsigned long address, } } -extern void ld_mmu_r23000(void); -extern void ld_mmu_r4xx0(void); -extern void ld_mmu_tx39(void); -extern void ld_mmu_r6000(void); -extern void ld_mmu_tfp(void); -extern void ld_mmu_andes(void); -extern void ld_mmu_sb1(void); +#define __weak __attribute__((weak)) + +static char cache_panic[] __initdata = "Yeee, unsupported cache architecture."; void __init cpu_cache_init(void) { - if (cpu_has_4ktlb) { -#if defined(CONFIG_CPU_R4X00) || defined(CONFIG_CPU_VR41XX) || \ - defined(CONFIG_CPU_R4300) || defined(CONFIG_CPU_R5000) || \ - defined(CONFIG_CPU_NEVADA) || defined(CONFIG_CPU_R5432) || \ - defined(CONFIG_CPU_R5500) || defined(CONFIG_CPU_MIPS32_R1) || \ - defined(CONFIG_CPU_MIPS64_R1) || defined(CONFIG_CPU_TX49XX) || \ - defined(CONFIG_CPU_RM7000) || defined(CONFIG_CPU_RM9000) - ld_mmu_r4xx0(); -#endif - } else switch (current_cpu_data.cputype) { -#ifdef CONFIG_CPU_R3000 - case CPU_R2000: - case CPU_R3000: - case CPU_R3000A: - case CPU_R3081E: - ld_mmu_r23000(); - break; -#endif -#ifdef CONFIG_CPU_TX39XX - case CPU_TX3912: - case CPU_TX3922: - case CPU_TX3927: - ld_mmu_tx39(); - break; -#endif -#ifdef CONFIG_CPU_R10000 - case CPU_R10000: - case CPU_R12000: - ld_mmu_r4xx0(); - break; -#endif -#ifdef CONFIG_CPU_SB1 - case CPU_SB1: - ld_mmu_sb1(); - break; -#endif - - case CPU_R8000: - panic("R8000 is unsupported"); - break; - - default: - panic("Yeee, unsupported cache architecture."); + if (cpu_has_3k_cache) { + extern void __weak r3k_cache_init(void); + + r3k_cache_init(); + return; + } + if (cpu_has_6k_cache) { + extern void __weak r6k_cache_init(void); + + r6k_cache_init(); + return; } + if (cpu_has_4k_cache) { + extern void __weak r4k_cache_init(void); + + r4k_cache_init(); + return; + } + if (cpu_has_8k_cache) { + extern void __weak r8k_cache_init(void); + + r8k_cache_init(); + return; + } + if (cpu_has_tx39_cache) { + extern void __weak tx39_cache_init(void); + + tx39_cache_init(); + return; + } + if (cpu_has_sb1_cache) { + extern void __weak sb1_cache_init(void); + + sb1_cache_init(); + return; + } + + panic(cache_panic); } |