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authorRalf Baechle <ralf@linux-mips.org>2009-04-19 03:21:22 +0200
committerRalf Baechle <ralf@linux-mips.org>2009-05-14 13:50:26 +0100
commit47740eb887796608fb4c629aa6b8507a2fb6c0eb (patch)
tree3b772b4b5f3a09899ec27c131cfdace411c75d74 /arch/mips
parent5d57c31e5790d44905af0459a21086dbad167d26 (diff)
downloadop-kernel-dev-47740eb887796608fb4c629aa6b8507a2fb6c0eb.zip
op-kernel-dev-47740eb887796608fb4c629aa6b8507a2fb6c0eb.tar.gz
MIPS: Enable CLO / CLZ instructions via separate CPU property
This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do not implement the full MIPS32 / MIPS64 architecture. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips')
-rw-r--r--arch/mips/include/asm/bitops.h4
-rw-r--r--arch/mips/include/asm/cpu-features.h9
2 files changed, 11 insertions, 2 deletions
diff --git a/arch/mips/include/asm/bitops.h b/arch/mips/include/asm/bitops.h
index bac4a96..b1e9e97 100644
--- a/arch/mips/include/asm/bitops.h
+++ b/arch/mips/include/asm/bitops.h
@@ -567,7 +567,7 @@ static inline unsigned long __fls(unsigned long word)
int num;
if (BITS_PER_LONG == 32 &&
- __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
+ __builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__(
" .set push \n"
" .set mips32 \n"
@@ -644,7 +644,7 @@ static inline int fls(int x)
{
int r;
- if (__builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r) {
+ if (__builtin_constant_p(cpu_has_clo_clz) && cpu_has_clo_clz) {
__asm__("clz %0, %1" : "=r" (x) : "r" (x));
return 32 - x;
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index a0d14f8..c0047f8 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -147,6 +147,15 @@
#define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \
cpu_has_mips64r1 | cpu_has_mips64r2)
+/*
+ * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other
+ * pre-MIPS32/MIPS53 processors have CLO, CLZ. For 64-bit kernels
+ * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ.
+ */
+# ifndef cpu_has_clo_clz
+# define cpu_has_clo_clz cpu_has_mips_r
+# endif
+
#ifndef cpu_has_dsp
#define cpu_has_dsp (cpu_data[0].ases & MIPS_ASE_DSP)
#endif
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