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| author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2007-11-27 19:31:33 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2008-01-29 10:14:58 +0000 |
| commit | c7c6b39050aed4af913c17970ebfb592bae757fc (patch) | |
| tree | faaad45cd4b3ef2f582c6b47a5082e9eee2853fd /arch/mips/sibyte | |
| parent | 930bff882296c02ca81db108672ef4ca06c37db5 (diff) | |
| download | op-kernel-dev-c7c6b39050aed4af913c17970ebfb592bae757fc.zip op-kernel-dev-c7c6b39050aed4af913c17970ebfb592bae757fc.tar.gz | |
[MIPS] Use correct dma flushing in dma_cache_sync()
Not cache coherent R10k systems (like IP28) need to do real cache
invalidates in dma_cache_sync().
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte')
0 files changed, 0 insertions, 0 deletions
