diff options
| author | Mark Mason <mason@broadcom.com> | 2006-10-10 17:03:10 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-10-11 19:30:59 +0100 |
| commit | 472f291df59fc1c5eb3ade74a50bfa222030e736 (patch) | |
| tree | 1ea4b1a03af63b7db42e71ab0366f227d0e5c78b /arch/mips/sibyte/bcm1480 | |
| parent | 9b95e629eab59ee140fe2b17bbd7fea6821c6085 (diff) | |
| download | op-kernel-dev-472f291df59fc1c5eb3ade74a50bfa222030e736.zip op-kernel-dev-472f291df59fc1c5eb3ade74a50bfa222030e736.tar.gz | |
[MIPS] Fix compilation warnings in arch/mips/sibyte/bcm1480/smp.c
Signed-off-by: Mark Mason <mason@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/sibyte/bcm1480')
| -rw-r--r-- | arch/mips/sibyte/bcm1480/smp.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index 6eac36d..bf32827 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -34,21 +34,21 @@ extern void smp_call_function_interrupt(void); * independent of board/firmware */ -static void *mailbox_0_set_regs[] = { +static volatile void *mailbox_0_set_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_SET_CPU), }; -static void *mailbox_0_clear_regs[] = { +static volatile void *mailbox_0_clear_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), IOADDR(A_BCM1480_IMR_CPU3_BASE + R_BCM1480_IMR_MAILBOX_0_CLR_CPU), }; -static void *mailbox_0_regs[] = { +static volatile void *mailbox_0_regs[] = { IOADDR(A_BCM1480_IMR_CPU0_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR(A_BCM1480_IMR_CPU1_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), IOADDR(A_BCM1480_IMR_CPU2_BASE + R_BCM1480_IMR_MAILBOX_0_CPU), |
