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authorPaul Burton <paul.burton@imgtec.com>2013-12-02 16:48:37 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-01-23 13:02:35 +0100
commitae0d7cbc99890b3a417a5705763784b8551a10d6 (patch)
tree5cad4268f616744749f6ea23e5ce406ecd2aec35 /arch/mips/pci
parenta87ea88d8f6c7ce5551b3761f8db5a4341c8b25d (diff)
downloadop-kernel-dev-ae0d7cbc99890b3a417a5705763784b8551a10d6.zip
op-kernel-dev-ae0d7cbc99890b3a417a5705763784b8551a10d6.tar.gz
MIPS: Malta: mux & enable SERIRQ interrupt
This patch causes the kernel to mux the SERIRQ interrupt to the SERIRQ pin of the PIIX4 and to enable that interrupt. The kernel depends upon the interrupt when using the SuperIO UARTs (ttyS0 & ttyS1) but previously would not configure it, instead relying upon the bootloader having done so. If that is not the case then the typical result is that the system appears to hang once it reaches userland as no output is displayed on the UART. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6182/
Diffstat (limited to 'arch/mips/pci')
-rw-r--r--arch/mips/pci/fixup-malta.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c
index df36e23..7a0eda7 100644
--- a/arch/mips/pci/fixup-malta.c
+++ b/arch/mips/pci/fixup-malta.c
@@ -54,6 +54,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev)
static void malta_piix_func0_fixup(struct pci_dev *pdev)
{
unsigned char reg_val;
+ u32 reg_val32;
/* PIIX PIRQC[A:D] irq mappings */
static int piixirqmap[PIIX4_FUNC0_PIRQRC_IRQ_ROUTING_MAX] = {
0, 0, 0, 3,
@@ -83,6 +84,16 @@ static void malta_piix_func0_fixup(struct pci_dev *pdev)
pci_write_config_byte(pdev, PIIX4_FUNC0_TOM, reg_val |
PIIX4_FUNC0_TOM_TOP_OF_MEMORY_MASK);
}
+
+ /* Mux SERIRQ to its pin */
+ pci_read_config_dword(pdev, PIIX4_FUNC0_GENCFG, &reg_val32);
+ pci_write_config_dword(pdev, PIIX4_FUNC0_GENCFG,
+ reg_val32 | PIIX4_FUNC0_GENCFG_SERIRQ);
+
+ /* Enable SERIRQ */
+ pci_read_config_byte(pdev, PIIX4_FUNC0_SERIRQC, &reg_val);
+ reg_val |= PIIX4_FUNC0_SERIRQC_EN | PIIX4_FUNC0_SERIRQC_CONT;
+ pci_write_config_byte(pdev, PIIX4_FUNC0_SERIRQC, reg_val);
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0,
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