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| author | Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> | 2014-03-04 13:34:43 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-26 23:09:22 +0100 |
| commit | f36c4720fca325579faddc880d4e178e4ccbda88 (patch) | |
| tree | 201608d0ba6b8b705ea20f9c64fc02364b402cdf /arch/mips/oprofile | |
| parent | 4975b86add254e1c706c82cded06ca2911f90ae3 (diff) | |
| download | op-kernel-dev-f36c4720fca325579faddc880d4e178e4ccbda88.zip op-kernel-dev-f36c4720fca325579faddc880d4e178e4ccbda88.tar.gz | |
MIPS: Add support for the M5150 processor
The M5150 core is a 32-bit MIPS RISC which implements the
MIPS Architecture Release-5 in a 5-stage pipeline.
In addition, it includes the MIPS Architecture Virtualization Module
that enables virtualization of operating systems,
which provides a scalable, trusted, and secure execution environment.
Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6596/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/oprofile')
| -rw-r--r-- | arch/mips/oprofile/common.c | 1 | ||||
| -rw-r--r-- | arch/mips/oprofile/op_model_mipsxx.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index e4ca70b..e747324 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -90,6 +90,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_INTERAPTIV: case CPU_PROAPTIV: case CPU_P5600: + case CPU_M5150: case CPU_LOONGSON1: case CPU_SB1: case CPU_SB1A: diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c index 9797493..42821ae 100644 --- a/arch/mips/oprofile/op_model_mipsxx.c +++ b/arch/mips/oprofile/op_model_mipsxx.c @@ -389,6 +389,10 @@ static int __init mipsxx_init(void) op_model_mipsxx_ops.cpu_type = "mips/P5600"; break; + case CPU_M5150: + op_model_mipsxx_ops.cpu_type = "mips/M5150"; + break; + case CPU_5KC: op_model_mipsxx_ops.cpu_type = "mips/5K"; break; |
