diff options
| author | Jayachandran C <jchandra@broadcom.com> | 2013-12-21 16:52:13 +0530 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-01-24 22:39:46 +0100 |
| commit | c24a8a7a99885d5b986f38f6631f69e7794a3e5e (patch) | |
| tree | a0d6702fc1c45cba157a5734215c509fa4b216c6 /arch/mips/netlogic/xlp/nlm_hal.c | |
| parent | 27547abf36af7964b53a8c9265e266df692d4806 (diff) | |
| download | op-kernel-dev-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.zip op-kernel-dev-c24a8a7a99885d5b986f38f6631f69e7794a3e5e.tar.gz | |
MIPS: Netlogic: Add MSI support for XLP
Add MSI chip and MSIX chip definitions.
For MSI, we map the link interrupt to a MSI link IRQ which will
do a second level of dispatch based on the MSI status register.
The MSI chip definitions use the MSI enable register to enable
and disable the MSI irqs.
For MSI-X, we split the 32 available MSI-X vectors across the
four PCIe links (8 each). These PIC interrupts generate an IRQ
per link which uses a second level dispatch as well.
The MSI-X chip definition uses the standard functions to enable
and disable interrupts.
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/6270/
Diffstat (limited to 'arch/mips/netlogic/xlp/nlm_hal.c')
| -rw-r--r-- | arch/mips/netlogic/xlp/nlm_hal.c | 12 |
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/mips/netlogic/xlp/nlm_hal.c b/arch/mips/netlogic/xlp/nlm_hal.c index 56c50ba..5693021 100644 --- a/arch/mips/netlogic/xlp/nlm_hal.c +++ b/arch/mips/netlogic/xlp/nlm_hal.c @@ -135,9 +135,17 @@ int nlm_irq_to_irt(int irq) case PIC_I2C_3_IRQ: irt = irt + 3; break; } - } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) { + } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) && + irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) { /* HW bug, PCI IRT entries are bad on early silicon, fix */ - irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ); + irt = PIC_IRT_PCIE_LINK_INDEX(irq - + PIC_PCIE_LINK_LEGACY_IRQ_BASE); + } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) && + irq <= PIC_PCIE_LINK_MSI_IRQ(3)) { + irt = -2; + } else if (irq >= PIC_PCIE_MSIX_IRQ(0) && + irq <= PIC_PCIE_MSIX_IRQ(3)) { + irt = -2; } else { irt = -1; } |
