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| author | Huacai Chen <chenhc@lemote.com> | 2014-03-21 18:44:00 +0800 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-31 18:17:12 +0200 |
| commit | c579d310b9b22b4b9fedcdd720c8ac58c901e1e9 (patch) | |
| tree | 2899124d69cd72f44ecf3006d561c7093120a3c4 /arch/mips/mm/tlb-r4k.c | |
| parent | 152ebb44eff3c2dae0fb7d5b19c3f65e7c8d3493 (diff) | |
| download | op-kernel-dev-c579d310b9b22b4b9fedcdd720c8ac58c901e1e9.zip op-kernel-dev-c579d310b9b22b4b9fedcdd720c8ac58c901e1e9.tar.gz | |
MIPS: Loongson: Add basic Loongson-3 CPU support
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen <chenhc@lemote.com>
Signed-off-by: Hongliang Tao <taohl@lemote.com>
Signed-off-by: Hua Yan <yanh@lemote.com>
Tested-by: Alex Smith <alex.smith@imgtec.com>
Reviewed-by: Alex Smith <alex.smith@imgtec.com>
Cc: John Crispin <john@phrozen.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang <zhangfx@lemote.com>
Cc: Zhangjin Wu <wuzhangjin@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/6630
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mm/tlb-r4k.c')
| -rw-r--r-- | arch/mips/mm/tlb-r4k.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index ae4ca24..eeaf50f 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -48,13 +48,14 @@ extern void build_tlb_refill_handler(void); #endif /* CONFIG_MIPS_MT_SMTC */ /* - * LOONGSON2 has a 4 entry itlb which is a subset of dtlb, - * unfortrunately, itlb is not totally transparent to software. + * LOONGSON2/3 has a 4 entry itlb which is a subset of dtlb, + * unfortunately, itlb is not totally transparent to software. */ static inline void flush_itlb(void) { switch (current_cpu_type()) { case CPU_LOONGSON2: + case CPU_LOONGSON3: write_c0_diag(4); break; default: |
