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author | Yoichi Yuasa <yuasa@linux-mips.org> | 2012-08-01 15:42:16 +0900 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2012-08-01 17:59:23 +0200 |
commit | 4b00951f6f2fd335f063e553b474fe4648b3307d (patch) | |
tree | 7742f40b0bf7195cb7505895305cbbf37b96b2f6 /arch/mips/loongson1/common | |
parent | 47cd7343f5467bf38d17a78eb99eaa8019e17007 (diff) | |
download | op-kernel-dev-4b00951f6f2fd335f063e553b474fe4648b3307d.zip op-kernel-dev-4b00951f6f2fd335f063e553b474fe4648b3307d.tar.gz |
MIPS: Loongson 1: more clk support and add select HAVE_CLK
This fixes a redefinition of clk_*:
arch/mips/loongson1/common/clock.c:23:13: error: redefinition of 'clk_get'
include/linux/clk.h:281:27: note: previous definition of 'clk_get' was here
arch/mips/loongson1/common/clock.c:41:15: error: redefinition of 'clk_get_rate'
include/linux/clk.h:302:29: note: previous definition of 'clk_get_rate' was here
make[3]: *** [arch/mips/loongson1/common/clock.o] Error 1
Signed-off-by: Yoichi Yuasa <yuasa@linux-mips.org>
Cc: linux-mips@linux-mips.org
Reviewed-by: John Crispin <blogic@openwrt.org>
Acked-by: Kelvin Cheung <keguang.zhang@gmail.com>
Patchwork: https://patchwork.linux-mips.org/patch/4143/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/loongson1/common')
-rw-r--r-- | arch/mips/loongson1/common/clock.c | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/mips/loongson1/common/clock.c b/arch/mips/loongson1/common/clock.c index 2d98fb0..1bbbbec 100644 --- a/arch/mips/loongson1/common/clock.c +++ b/arch/mips/loongson1/common/clock.c @@ -38,12 +38,28 @@ struct clk *clk_get(struct device *dev, const char *name) } EXPORT_SYMBOL(clk_get); +int clk_enable(struct clk *clk) +{ + return 0; +} +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_disable); + unsigned long clk_get_rate(struct clk *clk) { return clk->rate; } EXPORT_SYMBOL(clk_get_rate); +void clk_put(struct clk *clk) +{ +} +EXPORT_SYMBOL(clk_put); + static void pll_clk_init(struct clk *clk) { u32 pll; |