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| author | Masanari Iida <standby24x7@gmail.com> | 2012-11-23 01:05:13 +0900 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2012-12-13 18:15:23 +0100 |
| commit | d08be0dbe80d03dc132e017167795696f021b5a5 (patch) | |
| tree | 9f2887832b253be28c5ceb4ae235f96b8bf26063 /arch/mips/lantiq/xway | |
| parent | 0e2794b0b72f38d0dd5aa8474e22b1fe56fb8bd1 (diff) | |
| download | op-kernel-dev-d08be0dbe80d03dc132e017167795696f021b5a5.zip op-kernel-dev-d08be0dbe80d03dc132e017167795696f021b5a5.tar.gz | |
MIPS: Lantiq: Fix typo in "endianness" in dma.c
Correct spelling typo ENDIANESS to ENDIANNESS in arc/mips/lantiq/xway/dma.c
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Cc: trivial@kernel.org
Cc: linux-kernel@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/4613/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/lantiq/xway')
| -rw-r--r-- | arch/mips/lantiq/xway/dma.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c index 55d2c4f..0f7228d 100644 --- a/arch/mips/lantiq/xway/dma.c +++ b/arch/mips/lantiq/xway/dma.c @@ -48,7 +48,7 @@ #define DMA_CLK_DIV4 BIT(6) /* polling clock divider */ #define DMA_2W_BURST BIT(1) /* 2 word burst length */ #define DMA_MAX_CHANNEL 20 /* the soc has 20 channels */ -#define DMA_ETOP_ENDIANESS (0xf << 8) /* endianess swap etop channels */ +#define DMA_ETOP_ENDIANNESS (0xf << 8) /* endianness swap etop channels */ #define DMA_WEIGHT (BIT(17) | BIT(16)) /* default channel wheight */ #define ltq_dma_r32(x) ltq_r32(ltq_dma_membase + (x)) @@ -191,10 +191,10 @@ ltq_dma_init_port(int p) switch (p) { case DMA_PORT_ETOP: /* - * Tell the DMA engine to swap the endianess of data frames and + * Tell the DMA engine to swap the endianness of data frames and * drop packets if the channel arbitration fails. */ - ltq_dma_w32_mask(0, DMA_ETOP_ENDIANESS | DMA_PDEN, + ltq_dma_w32_mask(0, DMA_ETOP_ENDIANNESS | DMA_PDEN, LTQ_DMA_PCTRL); break; |
