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authorPaul Burton <paul.burton@imgtec.com>2014-03-27 10:57:30 +0000
committerRalf Baechle <ralf@linux-mips.org>2014-03-31 18:17:12 +0200
commit30ee615bb86ba640c9ec7f85fb95c1b0e31c41be (patch)
treeb756df1f38821bb46182fab185ebd2c4f5e0c86c /arch/mips/kernel
parent968a0734db05ad907bc8fffabdbe7da5e1e731f6 (diff)
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op-kernel-dev-30ee615bb86ba640c9ec7f85fb95c1b0e31c41be.tar.gz
MIPS: Fix core number detection for MT cores
In cores which implement the MT ASE, the CPUNum in the EBase register is a concatenation of the core number & the VPE ID within that core. In order to retrieve the correct core number CPUNum must be shifted appropriately to remove the VPE ID bits. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6666/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cpu-probe.c6
1 files changed, 5 insertions, 1 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index bd712c9..6e8fb85 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -23,6 +23,7 @@
#include <asm/cpu-type.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
+#include <asm/mipsmtregs.h>
#include <asm/msa.h>
#include <asm/watch.h>
#include <asm/elf.h>
@@ -421,8 +422,11 @@ static void decode_configs(struct cpuinfo_mips *c)
mips_probe_watch_registers(c);
#ifndef CONFIG_MIPS_CPS
- if (cpu_has_mips_r2)
+ if (cpu_has_mips_r2) {
c->core = read_c0_ebase() & 0x3ff;
+ if (cpu_has_mipsmt)
+ c->core >>= fls(core_nvpes()) - 1;
+ }
#endif
}
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