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| author | Paul Burton <paul.burton@imgtec.com> | 2014-07-09 12:51:05 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2014-07-30 20:49:36 +0200 |
| commit | 0fc0708a8a2e6ff5e9ab633185903831fe478994 (patch) | |
| tree | 069a9907d8ab37b65d2c03a6525f812a201d636f /arch/mips/kernel | |
| parent | c90e49f26466d1733558b8385f4755a6ee3ddafc (diff) | |
| download | op-kernel-dev-0fc0708a8a2e6ff5e9ab633185903831fe478994.zip op-kernel-dev-0fc0708a8a2e6ff5e9ab633185903831fe478994.tar.gz | |
MIPS: smp-cps: Fix entry code cache flush for systems with coherent I/O
The dma_cache_wback_inv function performs exactly as is required here,
unless the system has coherent I/O in which case it's a no-op. Call the
underlying cache writeback functions directly, which is arguably clearer
anyway given that the code doesn't actually have anything to do with
DMA in a strict sense.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/7282/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
| -rw-r--r-- | arch/mips/kernel/smp-cps.c | 10 |
1 files changed, 7 insertions, 3 deletions
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index f9b53b4..e6e16a1 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -14,13 +14,14 @@ #include <linux/smp.h> #include <linux/types.h> -#include <asm/cacheflush.h> +#include <asm/bcache.h> #include <asm/gic.h> #include <asm/mips-cm.h> #include <asm/mips-cpc.h> #include <asm/mips_mt.h> #include <asm/mipsregs.h> #include <asm/pm-cps.h> +#include <asm/r4kcache.h> #include <asm/smp-cps.h> #include <asm/time.h> #include <asm/uasm.h> @@ -132,8 +133,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) entry_code = (u32 *)&mips_cps_core_entry; UASM_i_LA(&entry_code, 3, (long)mips_cm_base); uasm_i_addiu(&entry_code, 16, 0, cca); - dma_cache_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); + blast_dcache_range((unsigned long)&mips_cps_core_entry, + (unsigned long)entry_code); + bc_wback_inv((unsigned long)&mips_cps_core_entry, + (void *)entry_code - (void *)&mips_cps_core_entry); + __sync(); /* Allocate core boot configuration structs */ mips_cps_core_bootcfg = kcalloc(ncores, sizeof(*mips_cps_core_bootcfg), |
