diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 17:33:02 +0100 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-07-10 17:33:02 +0100 |
commit | a36920200c5b89d56120a5e839fe4a603d51b16c (patch) | |
tree | aefb1fc4b0792ef788024fa596954a5689f15d0a /arch/mips/kernel | |
parent | d223a86154f8c66f5a380b17e1c8091d56f47cf8 (diff) | |
download | op-kernel-dev-a36920200c5b89d56120a5e839fe4a603d51b16c.zip op-kernel-dev-a36920200c5b89d56120a5e839fe4a603d51b16c.tar.gz |
[MIPS] Enable support for the userlocal hardware register
Which will cut down the cost of RDHWR $29 which is used to obtain the
TLS pointer and so far being emulated in software down to a single cycle
operation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/cpu-probe.c | 2 | ||||
-rw-r--r-- | arch/mips/kernel/syscall.c | 5 | ||||
-rw-r--r-- | arch/mips/kernel/traps.c | 9 |
3 files changed, 12 insertions, 4 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b12eeee..27fc184 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -588,6 +588,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c) c->options |= MIPS_CPU_VEIC; if (config3 & MIPS_CONF3_MT) c->ases |= MIPS_ASE_MIPSMT; + if (config3 & MIPS_CONF3_ULRI) + c->options |= MIPS_CPU_ULRI; return config3 & MIPS_CONF_M; } diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index 9dd5a2d..b947c61 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -272,9 +272,8 @@ asmlinkage int sys_set_thread_area(unsigned long addr) struct thread_info *ti = task_thread_info(current); ti->tp_value = addr; - - /* If some future MIPS implementation has this register in hardware, - * we will need to update it here (and in context switches). */ + if (cpu_has_userlocal) + write_c0_userlocal(addr); return 0; } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index c598e89..9b19a84 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1341,7 +1341,14 @@ void __init per_cpu_trap_init(void) set_c0_status(ST0_MX); #ifdef CONFIG_CPU_MIPSR2 - write_c0_hwrena (0x0000000f); /* Allow rdhwr to all registers */ + if (cpu_has_mips_r2) { + unsigned int enable = 0x0000000f; + + if (cpu_has_userlocal) + enable |= (1 << 29); + + write_c0_hwrena(enable); + } #endif #ifdef CONFIG_MIPS_MT_SMTC |