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authorLeonid Yegoshin <Leonid.Yegoshin@imgtec.com>2013-10-14 09:49:25 +0100
committerRalf Baechle <ralf@linux-mips.org>2014-01-22 20:18:57 +0100
commitf6ba061060f3442278d169a22db4469eed2ef1d3 (patch)
treec747bb6aa91e492e746fa1e8438afc2482da48d4 /arch/mips/kernel
parent6de20451857ed14a4eecc28d08f6de5925d1cf96 (diff)
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MIPS: Malta: Remove ttyS2 serial for CMP platforms
Commit 225ae5fd9a320e22841410049c3bdb6cf14a5841 "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6045/
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