diff options
author | Paul Burton <paul.burton@imgtec.com> | 2014-01-15 10:31:52 +0000 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2014-03-06 21:25:23 +0100 |
commit | 9c38cf44712af95a5ec3937d63faaea9b43eab9a (patch) | |
tree | 46413cc814e083de0b54ea3ac69420917d15d1fa /arch/mips/kernel | |
parent | 9f98f3dd0c518d9de02aebe0c25712b17ab3358d (diff) | |
download | op-kernel-dev-9c38cf44712af95a5ec3937d63faaea9b43eab9a.zip op-kernel-dev-9c38cf44712af95a5ec3937d63faaea9b43eab9a.tar.gz |
MIPS: Add CPC probe, access functions
This patch introduces code to probe for a MIPS Cluster Power Controller
& accessor functions to allow for easy register access. This support
code will be used by a subsequent patch.
Signed-off-by: Paul Burton <paul.burton@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/6361/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r-- | arch/mips/kernel/Makefile | 1 | ||||
-rw-r--r-- | arch/mips/kernel/mips-cpc.c | 52 |
2 files changed, 53 insertions, 0 deletions
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index be56cd8..a6a8717 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -104,6 +104,7 @@ obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o obj-$(CONFIG_JUMP_LABEL) += jump_label.o obj-$(CONFIG_MIPS_CM) += mips-cm.o +obj-$(CONFIG_MIPS_CPC) += mips-cpc.o # # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c new file mode 100644 index 0000000..c9dc674 --- /dev/null +++ b/arch/mips/kernel/mips-cpc.c @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2013 Imagination Technologies + * Author: Paul Burton <paul.burton@imgtec.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/errno.h> + +#include <asm/mips-cm.h> +#include <asm/mips-cpc.h> + +void __iomem *mips_cpc_base; + +phys_t __weak mips_cpc_phys_base(void) +{ + u32 cpc_base; + + if (!mips_cm_present()) + return 0; + + if (!(read_gcr_cpc_status() & CM_GCR_CPC_STATUS_EX_MSK)) + return 0; + + /* If the CPC is already enabled, leave it so */ + cpc_base = read_gcr_cpc_base(); + if (cpc_base & CM_GCR_CPC_BASE_CPCEN_MSK) + return cpc_base & CM_GCR_CPC_BASE_CPCBASE_MSK; + + /* Otherwise, give it the default address & enable it */ + cpc_base = mips_cpc_default_phys_base(); + write_gcr_cpc_base(cpc_base | CM_GCR_CPC_BASE_CPCEN_MSK); + return cpc_base; +} + +int mips_cpc_probe(void) +{ + phys_t addr; + + addr = mips_cpc_phys_base(); + if (!addr) + return -ENODEV; + + mips_cpc_base = ioremap_nocache(addr, 0x8000); + if (!mips_cpc_base) + return -ENXIO; + + return 0; +} |