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authorJames Hogan <james.hogan@imgtec.com>2015-01-27 21:45:47 +0000
committerRalf Baechle <ralf@linux-mips.org>2015-03-31 12:04:12 +0200
commit19971c0bcb45f264c83cb2fd2bce50457bd17cc4 (patch)
treee20a24ff0fc188c1478d7cccb6c098e2fe8ba714 /arch/mips/kernel
parentc9d6c8b0eba2421b9bf812919bece0b82d923689 (diff)
downloadop-kernel-dev-19971c0bcb45f264c83cb2fd2bce50457bd17cc4.zip
op-kernel-dev-19971c0bcb45f264c83cb2fd2bce50457bd17cc4.tar.gz
MIPS: cevt-r4k: Move handle_perf_irq() out of header
Long ago, commit 8531a35e5e27 ("[MIPS] SMTC: Fix SMTC dyntick support.") moved handle_perf_irq() out of cevt-r4k.c into a header so it could be shared with cevt-smtc.c. Slightly less long ago, commit b633648c5ad3 ("MIPS: MT: Remove SMTC support") removed all traces of SMTC support, including cevt-smtc.c, leaving cevt-r4k.c once again the sole user of handle_perf_irq(), therefore move it back into cevt-r4k.c from the header. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9123/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel')
-rw-r--r--arch/mips/kernel/cevt-r4k.c18
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 82bd2b2..623f0bc 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -37,6 +37,24 @@ void mips_set_clock_mode(enum clock_event_mode mode,
DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
int cp0_timer_irq_installed;
+/*
+ * Possibly handle a performance counter interrupt.
+ * Return true if the timer interrupt should not be checked
+ */
+static inline int handle_perf_irq(int r2)
+{
+ /*
+ * The performance counter overflow interrupt may be shared with the
+ * timer interrupt (cp0_perfcount_irq < 0). If it is and a
+ * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
+ * and we can't reliably determine if a counter interrupt has also
+ * happened (!r2) then don't check for a timer interrupt.
+ */
+ return (cp0_perfcount_irq < 0) &&
+ perf_irq() == IRQ_HANDLED &&
+ !r2;
+}
+
irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
{
const int r2 = cpu_has_mips_r2_r6;
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