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| author | Ralf Baechle <ralf@linux-mips.org> | 2005-10-06 17:39:32 +0100 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 19:32:36 +0100 |
| commit | 101b3531a693ad890f33f2f04323592cd376616a (patch) | |
| tree | adb9410d492ee3dca0fd437191213a28e02edcf4 /arch/mips/kernel/ptrace.c | |
| parent | 8afcb5d82934c83fb01664ae00eaff9de1d8d340 (diff) | |
| download | op-kernel-dev-101b3531a693ad890f33f2f04323592cd376616a.zip op-kernel-dev-101b3531a693ad890f33f2f04323592cd376616a.tar.gz | |
Protect manipulation of c0_status against preemption and multithreading.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/kernel/ptrace.c')
| -rw-r--r-- | arch/mips/kernel/ptrace.c | 39 |
1 files changed, 31 insertions, 8 deletions
diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c index 122433f..fcceab8 100644 --- a/arch/mips/kernel/ptrace.c +++ b/arch/mips/kernel/ptrace.c @@ -33,6 +33,7 @@ #include <asm/dsp.h> #include <asm/fpu.h> #include <asm/mipsregs.h> +#include <asm/mipsmtregs.h> #include <asm/pgtable.h> #include <asm/page.h> #include <asm/system.h> @@ -126,10 +127,21 @@ int ptrace_getfpregs (struct task_struct *child, __u32 __user *data) __put_user (child->thread.fpu.hard.fcr31, data + 64); - flags = read_c0_status(); - __enable_fpu(); - __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); - write_c0_status(flags); + preempt_disable(); + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); + write_c0_status(flags); + evpe(vpflags); + } else { + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0" : "=r" (tmp)); + write_c0_status(flags); + } + preempt_enable(); __put_user (tmp, data + 65); } else { __put_user (child->thread.fpu.soft.fcr31, data + 64); @@ -284,10 +296,21 @@ asmlinkage int sys_ptrace(long request, long pid, long addr, long data) if (!cpu_has_fpu) break; - flags = read_c0_status(); - __enable_fpu(); - __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); - write_c0_status(flags); + preempt_disable(); + if (cpu_has_mipsmt) { + unsigned int vpflags = dvpe(); + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + evpe(vpflags); + } else { + flags = read_c0_status(); + __enable_fpu(); + __asm__ __volatile__("cfc1\t%0,$0": "=r" (tmp)); + write_c0_status(flags); + } + preempt_enable(); break; } case DSP_BASE ... DSP_BASE + 5: { |
