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authorDavid S. Miller <davem@davemloft.net>2008-10-11 12:39:35 -0700
committerDavid S. Miller <davem@davemloft.net>2008-10-11 12:39:35 -0700
commit56c5d900dbb8e042bfad035d18433476931d8f93 (patch)
tree00b793965beeef10db03e0ff021d2d965c410759 /arch/mips/include/asm/txx9tmr.h
parent4dd95b63ae25c5cad6986829b5e8788e9faa0330 (diff)
parentead9d23d803ea3a73766c3cb27bf7563ac8d7266 (diff)
downloadop-kernel-dev-56c5d900dbb8e042bfad035d18433476931d8f93.zip
op-kernel-dev-56c5d900dbb8e042bfad035d18433476931d8f93.tar.gz
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6
Conflicts: sound/core/memalloc.c
Diffstat (limited to 'arch/mips/include/asm/txx9tmr.h')
-rw-r--r--arch/mips/include/asm/txx9tmr.h67
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/mips/include/asm/txx9tmr.h b/arch/mips/include/asm/txx9tmr.h
new file mode 100644
index 0000000..67f70a8
--- /dev/null
+++ b/arch/mips/include/asm/txx9tmr.h
@@ -0,0 +1,67 @@
+/*
+ * include/asm-mips/txx9tmr.h
+ * TX39/TX49 timer controller definitions.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#ifndef __ASM_TXX9TMR_H
+#define __ASM_TXX9TMR_H
+
+#include <linux/types.h>
+
+struct txx9_tmr_reg {
+ u32 tcr;
+ u32 tisr;
+ u32 cpra;
+ u32 cprb;
+ u32 itmr;
+ u32 unused0[3];
+ u32 ccdr;
+ u32 unused1[3];
+ u32 pgmr;
+ u32 unused2[3];
+ u32 wtmr;
+ u32 unused3[43];
+ u32 trr;
+};
+
+/* TMTCR : Timer Control */
+#define TXx9_TMTCR_TCE 0x00000080
+#define TXx9_TMTCR_CCDE 0x00000040
+#define TXx9_TMTCR_CRE 0x00000020
+#define TXx9_TMTCR_ECES 0x00000008
+#define TXx9_TMTCR_CCS 0x00000004
+#define TXx9_TMTCR_TMODE_MASK 0x00000003
+#define TXx9_TMTCR_TMODE_ITVL 0x00000000
+#define TXx9_TMTCR_TMODE_PGEN 0x00000001
+#define TXx9_TMTCR_TMODE_WDOG 0x00000002
+
+/* TMTISR : Timer Int. Status */
+#define TXx9_TMTISR_TPIBS 0x00000004
+#define TXx9_TMTISR_TPIAS 0x00000002
+#define TXx9_TMTISR_TIIS 0x00000001
+
+/* TMITMR : Interval Timer Mode */
+#define TXx9_TMITMR_TIIE 0x00008000
+#define TXx9_TMITMR_TZCE 0x00000001
+
+/* TMWTMR : Watchdog Timer Mode */
+#define TXx9_TMWTMR_TWIE 0x00008000
+#define TXx9_TMWTMR_WDIS 0x00000080
+#define TXx9_TMWTMR_TWC 0x00000001
+
+void txx9_clocksource_init(unsigned long baseaddr,
+ unsigned int imbusclk);
+void txx9_clockevent_init(unsigned long baseaddr, int irq,
+ unsigned int imbusclk);
+void txx9_tmr_init(unsigned long baseaddr);
+
+#ifdef CONFIG_CPU_TX39XX
+#define TXX9_TIMER_BITS 24
+#else
+#define TXX9_TIMER_BITS 32
+#endif
+
+#endif /* __ASM_TXX9TMR_H */
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