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author | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-14 13:05:21 -0800 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2012-01-14 13:05:21 -0800 |
commit | 4964e0664c80680fa6b28ef91381c076a5b25c2c (patch) | |
tree | 62099c5aaeee7274bcc66bcfba35d479affa97cf /arch/mips/include/asm/octeon/octeon-feature.h | |
parent | 0a80939b3e6af4b0dc93bf88ec02fd7e90a16f1b (diff) | |
parent | 7bf6612e8a9d6a0b3b82e8e2611942be1258b307 (diff) | |
download | op-kernel-dev-4964e0664c80680fa6b28ef91381c076a5b25c2c.zip op-kernel-dev-4964e0664c80680fa6b28ef91381c076a5b25c2c.tar.gz |
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (119 commits)
MIPS: Delete unused function add_temporary_entry.
MIPS: Set default pci cache line size.
MIPS: Flush huge TLB
MIPS: Octeon: Remove SYS_SUPPORTS_HIGHMEM.
MIPS: Octeon: Add support for OCTEON II PCIe
MIPS: Octeon: Update PCI Latency timer and enable more error reporting.
MIPS: Alchemy: Update cpu-feature-overrides
MIPS: Alchemy: db1200: Improve PB1200 detection.
MIPS: Alchemy: merge Au1000 and Au1300-style IRQ controller code.
MIPS: Alchemy: chain IRQ controllers to MIPS IRQ controller
MIPS: Alchemy: irq: register pm at irq init time
MIPS: Alchemy: Touchscreen support on DB1100
MIPS: Alchemy: Hook up IrDA on DB1000/DB1100
net/irda: convert au1k_ir to platform driver.
MIPS: Alchemy: remove unused board headers
MTD: nand: make au1550nd.c a platform_driver
MIPS: Netlogic: Mark Netlogic chips as SMT capable
MIPS: Netlogic: Add support for XLP 3XX cores
MIPS: Netlogic: Merge some of XLR/XLP wakup code
MIPS: Netlogic: Add default XLP config.
...
Fix up trivial conflicts in arch/mips/kernel/{perf_event_mipsxx.c,
traps.c} and drivers/tty/serial/Makefile
Diffstat (limited to 'arch/mips/include/asm/octeon/octeon-feature.h')
-rw-r--r-- | arch/mips/include/asm/octeon/octeon-feature.h | 114 |
1 files changed, 105 insertions, 9 deletions
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index cba6fbe..8008da2 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -31,8 +31,14 @@ #ifndef __OCTEON_FEATURE_H__ #define __OCTEON_FEATURE_H__ +#include <asm/octeon/cvmx-mio-defs.h> +#include <asm/octeon/cvmx-rnm-defs.h> enum octeon_feature { + /* CN68XX uses port kinds for packet interface */ + OCTEON_FEATURE_PKND, + /* CN68XX has different fields in word0 - word2 */ + OCTEON_FEATURE_CN68XX_WQE, /* * Octeon models in the CN5XXX family and higher support * atomic add instructions to memory (saa/saad). @@ -42,8 +48,13 @@ enum octeon_feature { OCTEON_FEATURE_ZIP, /* Does this Octeon support crypto acceleration using COP2? */ OCTEON_FEATURE_CRYPTO, + OCTEON_FEATURE_DORM_CRYPTO, /* Does this Octeon support PCI express? */ OCTEON_FEATURE_PCIE, + /* Does this Octeon support SRIOs */ + OCTEON_FEATURE_SRIO, + /* Does this Octeon support Interlaken */ + OCTEON_FEATURE_ILK, /* Some Octeon models support internal memory for storing * cryptographic keys */ OCTEON_FEATURE_KEY_MEMORY, @@ -64,6 +75,15 @@ enum octeon_feature { /* Octeon MDIO block supports clause 45 transactions for 10 * Gig support */ OCTEON_FEATURE_MDIO_CLAUSE_45, + /* + * CN52XX and CN56XX used a block named NPEI for PCIe + * access. Newer chips replaced this with SLI+DPI. + */ + OCTEON_FEATURE_NPEI, + OCTEON_FEATURE_HFA, + OCTEON_FEATURE_DFM, + OCTEON_FEATURE_CIU2, + OCTEON_MAX_FEATURE }; static inline int cvmx_fuse_read(int fuse); @@ -96,30 +116,78 @@ static inline int octeon_has_feature(enum octeon_feature feature) return !cvmx_fuse_read(121); case OCTEON_FEATURE_CRYPTO: - return !cvmx_fuse_read(90); + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat2 fus_2; + fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); + if (fus_2.s.nocrypto || fus_2.s.nomul) { + return 0; + } else if (!fus_2.s.dorm_crypto) { + return 1; + } else { + union cvmx_rnm_ctl_status st; + st.u64 = cvmx_read_csr(CVMX_RNM_CTL_STATUS); + return st.s.eer_val; + } + } else { + return !cvmx_fuse_read(90); + } + + case OCTEON_FEATURE_DORM_CRYPTO: + if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + union cvmx_mio_fus_dat2 fus_2; + fus_2.u64 = cvmx_read_csr(CVMX_MIO_FUS_DAT2); + return !fus_2.s.nocrypto && !fus_2.s.nomul && fus_2.s.dorm_crypto; + } else { + return 0; + } case OCTEON_FEATURE_PCIE: - case OCTEON_FEATURE_MGMT_PORT: - case OCTEON_FEATURE_RAID: return OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX); + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_SRIO: + return OCTEON_IS_MODEL(OCTEON_CN63XX) + || OCTEON_IS_MODEL(OCTEON_CN66XX); + + case OCTEON_FEATURE_ILK: + return (OCTEON_IS_MODEL(OCTEON_CN68XX)); case OCTEON_FEATURE_KEY_MEMORY: + return OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + case OCTEON_FEATURE_LED_CONTROLLER: return OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN56XX); + case OCTEON_FEATURE_TRA: return !(OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); + case OCTEON_FEATURE_MGMT_PORT: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + + case OCTEON_FEATURE_RAID: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX); + case OCTEON_FEATURE_USB: return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)); + case OCTEON_FEATURE_NO_WPTR: return (OCTEON_IS_MODEL(OCTEON_CN56XX) - || OCTEON_IS_MODEL(OCTEON_CN52XX)) - && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) - && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + || OCTEON_IS_MODEL(OCTEON_CN52XX) + || OCTEON_IS_MODEL(OCTEON_CN6XXX)) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + case OCTEON_FEATURE_DFA: if (!OCTEON_IS_MODEL(OCTEON_CN38XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) @@ -127,14 +195,42 @@ static inline int octeon_has_feature(enum octeon_feature feature) return 0; else if (OCTEON_IS_MODEL(OCTEON_CN3020)) return 0; - else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) - return 1; else return !cvmx_fuse_read(120); + + case OCTEON_FEATURE_HFA: + if (!OCTEON_IS_MODEL(OCTEON_CN6XXX)) + return 0; + else + return !cvmx_fuse_read(90); + + case OCTEON_FEATURE_DFM: + if (!(OCTEON_IS_MODEL(OCTEON_CN63XX) + || OCTEON_IS_MODEL(OCTEON_CN66XX))) + return 0; + else + return !cvmx_fuse_read(90); + case OCTEON_FEATURE_MDIO_CLAUSE_45: return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)); + + case OCTEON_FEATURE_NPEI: + return OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX); + + case OCTEON_FEATURE_PKND: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CN68XX_WQE: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + case OCTEON_FEATURE_CIU2: + return OCTEON_IS_MODEL(OCTEON_CN68XX); + + default: + break; } return 0; } |