Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS update from Ralf Baechle:
 "This is the MIPS update for 3.7.

  A fair chunk of them are platform updates to the Cavium Octeon SOC
  (which involves machine generated header files of considerable size),
  Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
  platforms.

  Support for the commercial MIPS simulator MIPSsim has been removed as
  MIPS Technologies is shifting away from this product and Qemu is
  offering various more powerful platforms.  The generic MIPS code can
  now also probe for no-execute / write-only TLB features implemented
  without the full SmartMIPS extension as permitted by the latest MIPS
  processor architecture.  Lots of small changes to generic code."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
  MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
  MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
  MIPS: BCM63XX: Properly handle mac address octet overflow
  MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
  MIPS: Replace `-' in defconfig filename wth `_' for consistency.
  MIPS: Wire kcmp syscall.
  MIPS: MIPSsim: Remove the MIPSsim platform.
  MIPS: NOTIFY_RESUME is not needed in TIF masks
  MIPS: Merge the identical "return from syscall" per-ABI code
  MIPS: Unobfuscate _TIF..._MASK
  MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
  MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
  MIPS: Add base architecture support for RI and XI.
  MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
  MIPS: uasm: Add INS and EXT instructions.
  MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
  MIPS: Make VPE count to be one-based.
  MIPS: Add new end of interrupt functionality for GIC.
  MIPS: Add EIC support for GIC.
  MIPS: Code clean-ups for the GIC.
  ...

1 files changed, 1350 insertions, 1 deletions

diff --git a/arch/mips/include/asm/octeon/cvmx-sli-defs.h b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
index 7c6c901..e697c2f 100644
--- a/arch/mips/include/asm/octeon/cvmx-sli-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-sli-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2011 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -127,6 +127,7 @@
 union cvmx_sli_bist_status {
 	uint64_t u64;
 	struct cvmx_sli_bist_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t ncb_req:1;
 		uint64_t n2p0_c:1;
@@ -153,8 +154,37 @@ union cvmx_sli_bist_status {
 		uint64_t dsi0_0:1;
 		uint64_t msi:1;
 		uint64_t ncb_cmd:1;
+#else
+		uint64_t ncb_cmd:1;
+		uint64_t msi:1;
+		uint64_t dsi0_0:1;
+		uint64_t dsi0_1:1;
+		uint64_t dsi1_0:1;
+		uint64_t dsi1_1:1;
+		uint64_t reserved_6_8:3;
+		uint64_t p2n1_p1:1;
+		uint64_t p2n1_p0:1;
+		uint64_t p2n1_n:1;
+		uint64_t p2n1_c1:1;
+		uint64_t p2n1_c0:1;
+		uint64_t p2n0_p1:1;
+		uint64_t p2n0_p0:1;
+		uint64_t p2n0_n:1;
+		uint64_t p2n0_c1:1;
+		uint64_t p2n0_c0:1;
+		uint64_t reserved_19_24:6;
+		uint64_t cpl_p1:1;
+		uint64_t cpl_p0:1;
+		uint64_t n2p1_o:1;
+		uint64_t n2p1_c:1;
+		uint64_t n2p0_o:1;
+		uint64_t n2p0_c:1;
+		uint64_t ncb_req:1;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_bist_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_31_63:33;
 		uint64_t n2p0_c:1;
 		uint64_t n2p0_o:1;
@@ -179,8 +209,35 @@ union cvmx_sli_bist_status {
 		uint64_t dsi0_0:1;
 		uint64_t msi:1;
 		uint64_t ncb_cmd:1;
+#else
+		uint64_t ncb_cmd:1;
+		uint64_t msi:1;
+		uint64_t dsi0_0:1;
+		uint64_t dsi0_1:1;
+		uint64_t dsi1_0:1;
+		uint64_t dsi1_1:1;
+		uint64_t reserved_6_8:3;
+		uint64_t p2n1_p1:1;
+		uint64_t p2n1_p0:1;
+		uint64_t p2n1_n:1;
+		uint64_t p2n1_c1:1;
+		uint64_t p2n1_c0:1;
+		uint64_t p2n0_p1:1;
+		uint64_t p2n0_p0:1;
+		uint64_t p2n0_n:1;
+		uint64_t p2n0_c1:1;
+		uint64_t p2n0_c0:1;
+		uint64_t reserved_19_24:6;
+		uint64_t cpl_p1:1;
+		uint64_t cpl_p0:1;
+		uint64_t reserved_27_28:2;
+		uint64_t n2p0_o:1;
+		uint64_t n2p0_c:1;
+		uint64_t reserved_31_63:33;
+#endif
 	} cn61xx;
 	struct cvmx_sli_bist_status_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_31_63:33;
 		uint64_t n2p0_c:1;
 		uint64_t n2p0_o:1;
@@ -206,16 +263,45 @@ union cvmx_sli_bist_status {
 		uint64_t dsi0_0:1;
 		uint64_t msi:1;
 		uint64_t ncb_cmd:1;
+#else
+		uint64_t ncb_cmd:1;
+		uint64_t msi:1;
+		uint64_t dsi0_0:1;
+		uint64_t dsi0_1:1;
+		uint64_t dsi1_0:1;
+		uint64_t dsi1_1:1;
+		uint64_t reserved_6_8:3;
+		uint64_t p2n1_p1:1;
+		uint64_t p2n1_p0:1;
+		uint64_t p2n1_n:1;
+		uint64_t p2n1_c1:1;
+		uint64_t p2n1_c0:1;
+		uint64_t p2n0_p1:1;
+		uint64_t p2n0_p0:1;
+		uint64_t p2n0_n:1;
+		uint64_t p2n0_c1:1;
+		uint64_t p2n0_c0:1;
+		uint64_t reserved_19_24:6;
+		uint64_t cpl_p1:1;
+		uint64_t cpl_p0:1;
+		uint64_t n2p1_o:1;
+		uint64_t n2p1_c:1;
+		uint64_t n2p0_o:1;
+		uint64_t n2p0_c:1;
+		uint64_t reserved_31_63:33;
+#endif
 	} cn63xx;
 	struct cvmx_sli_bist_status_cn63xx cn63xxp1;
 	struct cvmx_sli_bist_status_cn61xx cn66xx;
 	struct cvmx_sli_bist_status_s cn68xx;
 	struct cvmx_sli_bist_status_s cn68xxp1;
+	struct cvmx_sli_bist_status_cn61xx cnf71xx;
 };
 
 union cvmx_sli_ctl_portx {
 	uint64_t u64;
 	struct cvmx_sli_ctl_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_22_63:42;
 		uint64_t intd:1;
 		uint64_t intc:1;
@@ -232,6 +318,24 @@ union cvmx_sli_ctl_portx {
 		uint64_t ptlp_ro:1;
 		uint64_t reserved_1_4:4;
 		uint64_t wait_com:1;
+#else
+		uint64_t wait_com:1;
+		uint64_t reserved_1_4:4;
+		uint64_t ptlp_ro:1;
+		uint64_t reserved_6_6:1;
+		uint64_t ctlp_ro:1;
+		uint64_t inta_map:2;
+		uint64_t intb_map:2;
+		uint64_t intc_map:2;
+		uint64_t intd_map:2;
+		uint64_t waitl_com:1;
+		uint64_t dis_port:1;
+		uint64_t inta:1;
+		uint64_t intb:1;
+		uint64_t intc:1;
+		uint64_t intd:1;
+		uint64_t reserved_22_63:42;
+#endif
 	} s;
 	struct cvmx_sli_ctl_portx_s cn61xx;
 	struct cvmx_sli_ctl_portx_s cn63xx;
@@ -239,36 +343,59 @@ union cvmx_sli_ctl_portx {
 	struct cvmx_sli_ctl_portx_s cn66xx;
 	struct cvmx_sli_ctl_portx_s cn68xx;
 	struct cvmx_sli_ctl_portx_s cn68xxp1;
+	struct cvmx_sli_ctl_portx_s cnf71xx;
 };
 
 union cvmx_sli_ctl_status {
 	uint64_t u64;
 	struct cvmx_sli_ctl_status_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_20_63:44;
 		uint64_t p1_ntags:6;
 		uint64_t p0_ntags:6;
 		uint64_t chip_rev:8;
+#else
+		uint64_t chip_rev:8;
+		uint64_t p0_ntags:6;
+		uint64_t p1_ntags:6;
+		uint64_t reserved_20_63:44;
+#endif
 	} s;
 	struct cvmx_sli_ctl_status_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_14_63:50;
 		uint64_t p0_ntags:6;
 		uint64_t chip_rev:8;
+#else
+		uint64_t chip_rev:8;
+		uint64_t p0_ntags:6;
+		uint64_t reserved_14_63:50;
+#endif
 	} cn61xx;
 	struct cvmx_sli_ctl_status_s cn63xx;
 	struct cvmx_sli_ctl_status_s cn63xxp1;
 	struct cvmx_sli_ctl_status_cn61xx cn66xx;
 	struct cvmx_sli_ctl_status_s cn68xx;
 	struct cvmx_sli_ctl_status_s cn68xxp1;
+	struct cvmx_sli_ctl_status_cn61xx cnf71xx;
 };
 
 union cvmx_sli_data_out_cnt {
 	uint64_t u64;
 	struct cvmx_sli_data_out_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_44_63:20;
 		uint64_t p1_ucnt:16;
 		uint64_t p1_fcnt:6;
 		uint64_t p0_ucnt:16;
 		uint64_t p0_fcnt:6;
+#else
+		uint64_t p0_fcnt:6;
+		uint64_t p0_ucnt:16;
+		uint64_t p1_fcnt:6;
+		uint64_t p1_ucnt:16;
+		uint64_t reserved_44_63:20;
+#endif
 	} s;
 	struct cvmx_sli_data_out_cnt_s cn61xx;
 	struct cvmx_sli_data_out_cnt_s cn63xx;
@@ -276,14 +403,21 @@ union cvmx_sli_data_out_cnt {
 	struct cvmx_sli_data_out_cnt_s cn66xx;
 	struct cvmx_sli_data_out_cnt_s cn68xx;
 	struct cvmx_sli_data_out_cnt_s cn68xxp1;
+	struct cvmx_sli_data_out_cnt_s cnf71xx;
 };
 
 union cvmx_sli_dbg_data {
 	uint64_t u64;
 	struct cvmx_sli_dbg_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t dsel_ext:1;
 		uint64_t data:17;
+#else
+		uint64_t data:17;
+		uint64_t dsel_ext:1;
+		uint64_t reserved_18_63:46;
+#endif
 	} s;
 	struct cvmx_sli_dbg_data_s cn61xx;
 	struct cvmx_sli_dbg_data_s cn63xx;
@@ -291,14 +425,21 @@ union cvmx_sli_dbg_data {
 	struct cvmx_sli_dbg_data_s cn66xx;
 	struct cvmx_sli_dbg_data_s cn68xx;
 	struct cvmx_sli_dbg_data_s cn68xxp1;
+	struct cvmx_sli_dbg_data_s cnf71xx;
 };
 
 union cvmx_sli_dbg_select {
 	uint64_t u64;
 	struct cvmx_sli_dbg_select_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_33_63:31;
 		uint64_t adbg_sel:1;
 		uint64_t dbg_sel:32;
+#else
+		uint64_t dbg_sel:32;
+		uint64_t adbg_sel:1;
+		uint64_t reserved_33_63:31;
+#endif
 	} s;
 	struct cvmx_sli_dbg_select_s cn61xx;
 	struct cvmx_sli_dbg_select_s cn63xx;
@@ -306,13 +447,19 @@ union cvmx_sli_dbg_select {
 	struct cvmx_sli_dbg_select_s cn66xx;
 	struct cvmx_sli_dbg_select_s cn68xx;
 	struct cvmx_sli_dbg_select_s cn68xxp1;
+	struct cvmx_sli_dbg_select_s cnf71xx;
 };
 
 union cvmx_sli_dmax_cnt {
 	uint64_t u64;
 	struct cvmx_sli_dmax_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_dmax_cnt_s cn61xx;
 	struct cvmx_sli_dmax_cnt_s cn63xx;
@@ -320,13 +467,19 @@ union cvmx_sli_dmax_cnt {
 	struct cvmx_sli_dmax_cnt_s cn66xx;
 	struct cvmx_sli_dmax_cnt_s cn68xx;
 	struct cvmx_sli_dmax_cnt_s cn68xxp1;
+	struct cvmx_sli_dmax_cnt_s cnf71xx;
 };
 
 union cvmx_sli_dmax_int_level {
 	uint64_t u64;
 	struct cvmx_sli_dmax_int_level_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t time:32;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t time:32;
+#endif
 	} s;
 	struct cvmx_sli_dmax_int_level_s cn61xx;
 	struct cvmx_sli_dmax_int_level_s cn63xx;
@@ -334,13 +487,19 @@ union cvmx_sli_dmax_int_level {
 	struct cvmx_sli_dmax_int_level_s cn66xx;
 	struct cvmx_sli_dmax_int_level_s cn68xx;
 	struct cvmx_sli_dmax_int_level_s cn68xxp1;
+	struct cvmx_sli_dmax_int_level_s cnf71xx;
 };
 
 union cvmx_sli_dmax_tim {
 	uint64_t u64;
 	struct cvmx_sli_dmax_tim_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t tim:32;
+#else
+		uint64_t tim:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_dmax_tim_s cn61xx;
 	struct cvmx_sli_dmax_tim_s cn63xx;
@@ -348,11 +507,13 @@ union cvmx_sli_dmax_tim {
 	struct cvmx_sli_dmax_tim_s cn66xx;
 	struct cvmx_sli_dmax_tim_s cn68xx;
 	struct cvmx_sli_dmax_tim_s cn68xxp1;
+	struct cvmx_sli_dmax_tim_s cnf71xx;
 };
 
 union cvmx_sli_int_enb_ciu {
 	uint64_t u64;
 	struct cvmx_sli_int_enb_ciu_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -399,8 +560,57 @@ union cvmx_sli_int_enb_ciu {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t reserved_18_19:2;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} s;
 	struct cvmx_sli_int_enb_ciu_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t sprt3_err:1;
@@ -446,8 +656,56 @@ union cvmx_sli_int_enb_ciu {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t reserved_18_19:2;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn61xx;
 	struct cvmx_sli_int_enb_ciu_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t reserved_58_59:2;
@@ -483,10 +741,48 @@ union cvmx_sli_int_enb_ciu {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t reserved_18_31:14;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn63xx;
 	struct cvmx_sli_int_enb_ciu_cn63xx cn63xxp1;
 	struct cvmx_sli_int_enb_ciu_cn61xx cn66xx;
 	struct cvmx_sli_int_enb_ciu_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -523,13 +819,53 @@ union cvmx_sli_int_enb_ciu {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t reserved_18_31:14;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t reserved_51_51:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} cn68xx;
 	struct cvmx_sli_int_enb_ciu_cn68xx cn68xxp1;
+	struct cvmx_sli_int_enb_ciu_cn61xx cnf71xx;
 };
 
 union cvmx_sli_int_enb_portx {
 	uint64_t u64;
 	struct cvmx_sli_int_enb_portx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -577,8 +913,58 @@ union cvmx_sli_int_enb_portx {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} s;
 	struct cvmx_sli_int_enb_portx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t sprt3_err:1;
@@ -625,8 +1011,57 @@ union cvmx_sli_int_enb_portx {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn61xx;
 	struct cvmx_sli_int_enb_portx_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t reserved_58_59:2;
@@ -664,10 +1099,50 @@ union cvmx_sli_int_enb_portx {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t reserved_20_31:12;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn63xx;
 	struct cvmx_sli_int_enb_portx_cn63xx cn63xxp1;
 	struct cvmx_sli_int_enb_portx_cn61xx cn66xx;
 	struct cvmx_sli_int_enb_portx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -706,13 +1181,55 @@ union cvmx_sli_int_enb_portx {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t reserved_20_31:12;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t reserved_51_51:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} cn68xx;
 	struct cvmx_sli_int_enb_portx_cn68xx cn68xxp1;
+	struct cvmx_sli_int_enb_portx_cn61xx cnf71xx;
 };
 
 union cvmx_sli_int_sum {
 	uint64_t u64;
 	struct cvmx_sli_int_sum_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -760,8 +1277,58 @@ union cvmx_sli_int_sum {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} s;
 	struct cvmx_sli_int_sum_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t sprt3_err:1;
@@ -808,8 +1375,57 @@ union cvmx_sli_int_sum {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t m2_up_b0:1;
+		uint64_t m2_up_wi:1;
+		uint64_t m2_un_b0:1;
+		uint64_t m2_un_wi:1;
+		uint64_t m3_up_b0:1;
+		uint64_t m3_up_wi:1;
+		uint64_t m3_un_b0:1;
+		uint64_t m3_un_wi:1;
+		uint64_t reserved_28_31:4;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t sprt2_err:1;
+		uint64_t sprt3_err:1;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn61xx;
 	struct cvmx_sli_int_sum_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_61_63:3;
 		uint64_t ill_pad:1;
 		uint64_t reserved_58_59:2;
@@ -847,10 +1463,50 @@ union cvmx_sli_int_sum {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t reserved_20_31:12;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t pin_bp:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t reserved_61_63:3;
+#endif
 	} cn63xx;
 	struct cvmx_sli_int_sum_cn63xx cn63xxp1;
 	struct cvmx_sli_int_sum_cn61xx cn66xx;
 	struct cvmx_sli_int_sum_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_62_63:2;
 		uint64_t pipe_err:1;
 		uint64_t ill_pad:1;
@@ -889,14 +1545,59 @@ union cvmx_sli_int_sum {
 		uint64_t bar0_to:1;
 		uint64_t reserved_1_1:1;
 		uint64_t rml_to:1;
+#else
+		uint64_t rml_to:1;
+		uint64_t reserved_1_1:1;
+		uint64_t bar0_to:1;
+		uint64_t iob2big:1;
+		uint64_t pcnt:1;
+		uint64_t ptime:1;
+		uint64_t reserved_6_7:2;
+		uint64_t m0_up_b0:1;
+		uint64_t m0_up_wi:1;
+		uint64_t m0_un_b0:1;
+		uint64_t m0_un_wi:1;
+		uint64_t m1_up_b0:1;
+		uint64_t m1_up_wi:1;
+		uint64_t m1_un_b0:1;
+		uint64_t m1_un_wi:1;
+		uint64_t mio_int0:1;
+		uint64_t mio_int1:1;
+		uint64_t mac0_int:1;
+		uint64_t mac1_int:1;
+		uint64_t reserved_20_31:12;
+		uint64_t dmafi:2;
+		uint64_t dcnt:2;
+		uint64_t dtime:2;
+		uint64_t reserved_38_47:10;
+		uint64_t pidbof:1;
+		uint64_t psldbof:1;
+		uint64_t pout_err:1;
+		uint64_t reserved_51_51:1;
+		uint64_t pgl_err:1;
+		uint64_t pdi_err:1;
+		uint64_t pop_err:1;
+		uint64_t pins_err:1;
+		uint64_t sprt0_err:1;
+		uint64_t sprt1_err:1;
+		uint64_t reserved_58_59:2;
+		uint64_t ill_pad:1;
+		uint64_t pipe_err:1;
+		uint64_t reserved_62_63:2;
+#endif
 	} cn68xx;
 	struct cvmx_sli_int_sum_cn68xx cn68xxp1;
+	struct cvmx_sli_int_sum_cn61xx cnf71xx;
 };
 
 union cvmx_sli_last_win_rdata0 {
 	uint64_t u64;
 	struct cvmx_sli_last_win_rdata0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_last_win_rdata0_s cn61xx;
 	struct cvmx_sli_last_win_rdata0_s cn63xx;
@@ -904,12 +1605,17 @@ union cvmx_sli_last_win_rdata0 {
 	struct cvmx_sli_last_win_rdata0_s cn66xx;
 	struct cvmx_sli_last_win_rdata0_s cn68xx;
 	struct cvmx_sli_last_win_rdata0_s cn68xxp1;
+	struct cvmx_sli_last_win_rdata0_s cnf71xx;
 };
 
 union cvmx_sli_last_win_rdata1 {
 	uint64_t u64;
 	struct cvmx_sli_last_win_rdata1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_last_win_rdata1_s cn61xx;
 	struct cvmx_sli_last_win_rdata1_s cn63xx;
@@ -917,29 +1623,41 @@ union cvmx_sli_last_win_rdata1 {
 	struct cvmx_sli_last_win_rdata1_s cn66xx;
 	struct cvmx_sli_last_win_rdata1_s cn68xx;
 	struct cvmx_sli_last_win_rdata1_s cn68xxp1;
+	struct cvmx_sli_last_win_rdata1_s cnf71xx;
 };
 
 union cvmx_sli_last_win_rdata2 {
 	uint64_t u64;
 	struct cvmx_sli_last_win_rdata2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_last_win_rdata2_s cn61xx;
 	struct cvmx_sli_last_win_rdata2_s cn66xx;
+	struct cvmx_sli_last_win_rdata2_s cnf71xx;
 };
 
 union cvmx_sli_last_win_rdata3 {
 	uint64_t u64;
 	struct cvmx_sli_last_win_rdata3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_last_win_rdata3_s cn61xx;
 	struct cvmx_sli_last_win_rdata3_s cn66xx;
+	struct cvmx_sli_last_win_rdata3_s cnf71xx;
 };
 
 union cvmx_sli_mac_credit_cnt {
 	uint64_t u64;
 	struct cvmx_sli_mac_credit_cnt_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_54_63:10;
 		uint64_t p1_c_d:1;
 		uint64_t p1_n_d:1;
@@ -953,10 +1671,26 @@ union cvmx_sli_mac_credit_cnt {
 		uint64_t p0_ccnt:8;
 		uint64_t p0_ncnt:8;
 		uint64_t p0_pcnt:8;
+#else
+		uint64_t p0_pcnt:8;
+		uint64_t p0_ncnt:8;
+		uint64_t p0_ccnt:8;
+		uint64_t p1_pcnt:8;
+		uint64_t p1_ncnt:8;
+		uint64_t p1_ccnt:8;
+		uint64_t p0_p_d:1;
+		uint64_t p0_n_d:1;
+		uint64_t p0_c_d:1;
+		uint64_t p1_p_d:1;
+		uint64_t p1_n_d:1;
+		uint64_t p1_c_d:1;
+		uint64_t reserved_54_63:10;
+#endif
 	} s;
 	struct cvmx_sli_mac_credit_cnt_s cn61xx;
 	struct cvmx_sli_mac_credit_cnt_s cn63xx;
 	struct cvmx_sli_mac_credit_cnt_cn63xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_48_63:16;
 		uint64_t p1_ccnt:8;
 		uint64_t p1_ncnt:8;
@@ -964,15 +1698,26 @@ union cvmx_sli_mac_credit_cnt {
 		uint64_t p0_ccnt:8;
 		uint64_t p0_ncnt:8;
 		uint64_t p0_pcnt:8;
+#else
+		uint64_t p0_pcnt:8;
+		uint64_t p0_ncnt:8;
+		uint64_t p0_ccnt:8;
+		uint64_t p1_pcnt:8;
+		uint64_t p1_ncnt:8;
+		uint64_t p1_ccnt:8;
+		uint64_t reserved_48_63:16;
+#endif
 	} cn63xxp1;
 	struct cvmx_sli_mac_credit_cnt_s cn66xx;
 	struct cvmx_sli_mac_credit_cnt_s cn68xx;
 	struct cvmx_sli_mac_credit_cnt_s cn68xxp1;
+	struct cvmx_sli_mac_credit_cnt_s cnf71xx;
 };
 
 union cvmx_sli_mac_credit_cnt2 {
 	uint64_t u64;
 	struct cvmx_sli_mac_credit_cnt2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_54_63:10;
 		uint64_t p3_c_d:1;
 		uint64_t p3_n_d:1;
@@ -986,34 +1731,68 @@ union cvmx_sli_mac_credit_cnt2 {
 		uint64_t p2_ccnt:8;
 		uint64_t p2_ncnt:8;
 		uint64_t p2_pcnt:8;
+#else
+		uint64_t p2_pcnt:8;
+		uint64_t p2_ncnt:8;
+		uint64_t p2_ccnt:8;
+		uint64_t p3_pcnt:8;
+		uint64_t p3_ncnt:8;
+		uint64_t p3_ccnt:8;
+		uint64_t p2_p_d:1;
+		uint64_t p2_n_d:1;
+		uint64_t p2_c_d:1;
+		uint64_t p3_p_d:1;
+		uint64_t p3_n_d:1;
+		uint64_t p3_c_d:1;
+		uint64_t reserved_54_63:10;
+#endif
 	} s;
 	struct cvmx_sli_mac_credit_cnt2_s cn61xx;
 	struct cvmx_sli_mac_credit_cnt2_s cn66xx;
+	struct cvmx_sli_mac_credit_cnt2_s cnf71xx;
 };
 
 union cvmx_sli_mac_number {
 	uint64_t u64;
 	struct cvmx_sli_mac_number_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_9_63:55;
 		uint64_t a_mode:1;
 		uint64_t num:8;
+#else
+		uint64_t num:8;
+		uint64_t a_mode:1;
+		uint64_t reserved_9_63:55;
+#endif
 	} s;
 	struct cvmx_sli_mac_number_s cn61xx;
 	struct cvmx_sli_mac_number_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_8_63:56;
 		uint64_t num:8;
+#else
+		uint64_t num:8;
+		uint64_t reserved_8_63:56;
+#endif
 	} cn63xx;
 	struct cvmx_sli_mac_number_s cn66xx;
 	struct cvmx_sli_mac_number_cn63xx cn68xx;
 	struct cvmx_sli_mac_number_cn63xx cn68xxp1;
+	struct cvmx_sli_mac_number_s cnf71xx;
 };
 
 union cvmx_sli_mem_access_ctl {
 	uint64_t u64;
 	struct cvmx_sli_mem_access_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_14_63:50;
 		uint64_t max_word:4;
 		uint64_t timer:10;
+#else
+		uint64_t timer:10;
+		uint64_t max_word:4;
+		uint64_t reserved_14_63:50;
+#endif
 	} s;
 	struct cvmx_sli_mem_access_ctl_s cn61xx;
 	struct cvmx_sli_mem_access_ctl_s cn63xx;
@@ -1021,11 +1800,13 @@ union cvmx_sli_mem_access_ctl {
 	struct cvmx_sli_mem_access_ctl_s cn66xx;
 	struct cvmx_sli_mem_access_ctl_s cn68xx;
 	struct cvmx_sli_mem_access_ctl_s cn68xxp1;
+	struct cvmx_sli_mem_access_ctl_s cnf71xx;
 };
 
 union cvmx_sli_mem_access_subidx {
 	uint64_t u64;
 	struct cvmx_sli_mem_access_subidx_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_43_63:21;
 		uint64_t zero:1;
 		uint64_t port:3;
@@ -1035,8 +1816,20 @@ union cvmx_sli_mem_access_subidx {
 		uint64_t wtype:2;
 		uint64_t rtype:2;
 		uint64_t reserved_0_29:30;
+#else
+		uint64_t reserved_0_29:30;
+		uint64_t rtype:2;
+		uint64_t wtype:2;
+		uint64_t esw:2;
+		uint64_t esr:2;
+		uint64_t nmerge:1;
+		uint64_t port:3;
+		uint64_t zero:1;
+		uint64_t reserved_43_63:21;
+#endif
 	} s;
 	struct cvmx_sli_mem_access_subidx_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_43_63:21;
 		uint64_t zero:1;
 		uint64_t port:3;
@@ -1046,11 +1839,23 @@ union cvmx_sli_mem_access_subidx {
 		uint64_t wtype:2;
 		uint64_t rtype:2;
 		uint64_t ba:30;
+#else
+		uint64_t ba:30;
+		uint64_t rtype:2;
+		uint64_t wtype:2;
+		uint64_t esw:2;
+		uint64_t esr:2;
+		uint64_t nmerge:1;
+		uint64_t port:3;
+		uint64_t zero:1;
+		uint64_t reserved_43_63:21;
+#endif
 	} cn61xx;
 	struct cvmx_sli_mem_access_subidx_cn61xx cn63xx;
 	struct cvmx_sli_mem_access_subidx_cn61xx cn63xxp1;
 	struct cvmx_sli_mem_access_subidx_cn61xx cn66xx;
 	struct cvmx_sli_mem_access_subidx_cn68xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_43_63:21;
 		uint64_t zero:1;
 		uint64_t port:3;
@@ -1061,14 +1866,31 @@ union cvmx_sli_mem_access_subidx {
 		uint64_t rtype:2;
 		uint64_t ba:28;
 		uint64_t reserved_0_1:2;
+#else
+		uint64_t reserved_0_1:2;
+		uint64_t ba:28;
+		uint64_t rtype:2;
+		uint64_t wtype:2;
+		uint64_t esw:2;
+		uint64_t esr:2;
+		uint64_t nmerge:1;
+		uint64_t port:3;
+		uint64_t zero:1;
+		uint64_t reserved_43_63:21;
+#endif
 	} cn68xx;
 	struct cvmx_sli_mem_access_subidx_cn68xx cn68xxp1;
+	struct cvmx_sli_mem_access_subidx_cn61xx cnf71xx;
 };
 
 union cvmx_sli_msi_enb0 {
 	uint64_t u64;
 	struct cvmx_sli_msi_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t enb:64;
+#else
 		uint64_t enb:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_enb0_s cn61xx;
 	struct cvmx_sli_msi_enb0_s cn63xx;
@@ -1076,12 +1898,17 @@ union cvmx_sli_msi_enb0 {
 	struct cvmx_sli_msi_enb0_s cn66xx;
 	struct cvmx_sli_msi_enb0_s cn68xx;
 	struct cvmx_sli_msi_enb0_s cn68xxp1;
+	struct cvmx_sli_msi_enb0_s cnf71xx;
 };
 
 union cvmx_sli_msi_enb1 {
 	uint64_t u64;
 	struct cvmx_sli_msi_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t enb:64;
+#else
 		uint64_t enb:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_enb1_s cn61xx;
 	struct cvmx_sli_msi_enb1_s cn63xx;
@@ -1089,12 +1916,17 @@ union cvmx_sli_msi_enb1 {
 	struct cvmx_sli_msi_enb1_s cn66xx;
 	struct cvmx_sli_msi_enb1_s cn68xx;
 	struct cvmx_sli_msi_enb1_s cn68xxp1;
+	struct cvmx_sli_msi_enb1_s cnf71xx;
 };
 
 union cvmx_sli_msi_enb2 {
 	uint64_t u64;
 	struct cvmx_sli_msi_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t enb:64;
+#else
 		uint64_t enb:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_enb2_s cn61xx;
 	struct cvmx_sli_msi_enb2_s cn63xx;
@@ -1102,12 +1934,17 @@ union cvmx_sli_msi_enb2 {
 	struct cvmx_sli_msi_enb2_s cn66xx;
 	struct cvmx_sli_msi_enb2_s cn68xx;
 	struct cvmx_sli_msi_enb2_s cn68xxp1;
+	struct cvmx_sli_msi_enb2_s cnf71xx;
 };
 
 union cvmx_sli_msi_enb3 {
 	uint64_t u64;
 	struct cvmx_sli_msi_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t enb:64;
+#else
 		uint64_t enb:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_enb3_s cn61xx;
 	struct cvmx_sli_msi_enb3_s cn63xx;
@@ -1115,12 +1952,17 @@ union cvmx_sli_msi_enb3 {
 	struct cvmx_sli_msi_enb3_s cn66xx;
 	struct cvmx_sli_msi_enb3_s cn68xx;
 	struct cvmx_sli_msi_enb3_s cn68xxp1;
+	struct cvmx_sli_msi_enb3_s cnf71xx;
 };
 
 union cvmx_sli_msi_rcv0 {
 	uint64_t u64;
 	struct cvmx_sli_msi_rcv0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t intr:64;
+#else
 		uint64_t intr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_rcv0_s cn61xx;
 	struct cvmx_sli_msi_rcv0_s cn63xx;
@@ -1128,12 +1970,17 @@ union cvmx_sli_msi_rcv0 {
 	struct cvmx_sli_msi_rcv0_s cn66xx;
 	struct cvmx_sli_msi_rcv0_s cn68xx;
 	struct cvmx_sli_msi_rcv0_s cn68xxp1;
+	struct cvmx_sli_msi_rcv0_s cnf71xx;
 };
 
 union cvmx_sli_msi_rcv1 {
 	uint64_t u64;
 	struct cvmx_sli_msi_rcv1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t intr:64;
+#else
 		uint64_t intr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_rcv1_s cn61xx;
 	struct cvmx_sli_msi_rcv1_s cn63xx;
@@ -1141,12 +1988,17 @@ union cvmx_sli_msi_rcv1 {
 	struct cvmx_sli_msi_rcv1_s cn66xx;
 	struct cvmx_sli_msi_rcv1_s cn68xx;
 	struct cvmx_sli_msi_rcv1_s cn68xxp1;
+	struct cvmx_sli_msi_rcv1_s cnf71xx;
 };
 
 union cvmx_sli_msi_rcv2 {
 	uint64_t u64;
 	struct cvmx_sli_msi_rcv2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t intr:64;
+#else
 		uint64_t intr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_rcv2_s cn61xx;
 	struct cvmx_sli_msi_rcv2_s cn63xx;
@@ -1154,12 +2006,17 @@ union cvmx_sli_msi_rcv2 {
 	struct cvmx_sli_msi_rcv2_s cn66xx;
 	struct cvmx_sli_msi_rcv2_s cn68xx;
 	struct cvmx_sli_msi_rcv2_s cn68xxp1;
+	struct cvmx_sli_msi_rcv2_s cnf71xx;
 };
 
 union cvmx_sli_msi_rcv3 {
 	uint64_t u64;
 	struct cvmx_sli_msi_rcv3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t intr:64;
+#else
 		uint64_t intr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_rcv3_s cn61xx;
 	struct cvmx_sli_msi_rcv3_s cn63xx;
@@ -1167,14 +2024,21 @@ union cvmx_sli_msi_rcv3 {
 	struct cvmx_sli_msi_rcv3_s cn66xx;
 	struct cvmx_sli_msi_rcv3_s cn68xx;
 	struct cvmx_sli_msi_rcv3_s cn68xxp1;
+	struct cvmx_sli_msi_rcv3_s cnf71xx;
 };
 
 union cvmx_sli_msi_rd_map {
 	uint64_t u64;
 	struct cvmx_sli_msi_rd_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_16_63:48;
 		uint64_t rd_int:8;
 		uint64_t msi_int:8;
+#else
+		uint64_t msi_int:8;
+		uint64_t rd_int:8;
+		uint64_t reserved_16_63:48;
+#endif
 	} s;
 	struct cvmx_sli_msi_rd_map_s cn61xx;
 	struct cvmx_sli_msi_rd_map_s cn63xx;
@@ -1182,12 +2046,17 @@ union cvmx_sli_msi_rd_map {
 	struct cvmx_sli_msi_rd_map_s cn66xx;
 	struct cvmx_sli_msi_rd_map_s cn68xx;
 	struct cvmx_sli_msi_rd_map_s cn68xxp1;
+	struct cvmx_sli_msi_rd_map_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1c_enb0 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1c_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t clr:64;
+#else
 		uint64_t clr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1c_enb0_s cn61xx;
 	struct cvmx_sli_msi_w1c_enb0_s cn63xx;
@@ -1195,12 +2064,17 @@ union cvmx_sli_msi_w1c_enb0 {
 	struct cvmx_sli_msi_w1c_enb0_s cn66xx;
 	struct cvmx_sli_msi_w1c_enb0_s cn68xx;
 	struct cvmx_sli_msi_w1c_enb0_s cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb0_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1c_enb1 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1c_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t clr:64;
+#else
 		uint64_t clr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1c_enb1_s cn61xx;
 	struct cvmx_sli_msi_w1c_enb1_s cn63xx;
@@ -1208,12 +2082,17 @@ union cvmx_sli_msi_w1c_enb1 {
 	struct cvmx_sli_msi_w1c_enb1_s cn66xx;
 	struct cvmx_sli_msi_w1c_enb1_s cn68xx;
 	struct cvmx_sli_msi_w1c_enb1_s cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb1_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1c_enb2 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1c_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t clr:64;
+#else
 		uint64_t clr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1c_enb2_s cn61xx;
 	struct cvmx_sli_msi_w1c_enb2_s cn63xx;
@@ -1221,12 +2100,17 @@ union cvmx_sli_msi_w1c_enb2 {
 	struct cvmx_sli_msi_w1c_enb2_s cn66xx;
 	struct cvmx_sli_msi_w1c_enb2_s cn68xx;
 	struct cvmx_sli_msi_w1c_enb2_s cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb2_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1c_enb3 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1c_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t clr:64;
+#else
 		uint64_t clr:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1c_enb3_s cn61xx;
 	struct cvmx_sli_msi_w1c_enb3_s cn63xx;
@@ -1234,12 +2118,17 @@ union cvmx_sli_msi_w1c_enb3 {
 	struct cvmx_sli_msi_w1c_enb3_s cn66xx;
 	struct cvmx_sli_msi_w1c_enb3_s cn68xx;
 	struct cvmx_sli_msi_w1c_enb3_s cn68xxp1;
+	struct cvmx_sli_msi_w1c_enb3_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1s_enb0 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1s_enb0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t set:64;
+#else
 		uint64_t set:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1s_enb0_s cn61xx;
 	struct cvmx_sli_msi_w1s_enb0_s cn63xx;
@@ -1247,12 +2136,17 @@ union cvmx_sli_msi_w1s_enb0 {
 	struct cvmx_sli_msi_w1s_enb0_s cn66xx;
 	struct cvmx_sli_msi_w1s_enb0_s cn68xx;
 	struct cvmx_sli_msi_w1s_enb0_s cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb0_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1s_enb1 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1s_enb1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t set:64;
+#else
 		uint64_t set:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1s_enb1_s cn61xx;
 	struct cvmx_sli_msi_w1s_enb1_s cn63xx;
@@ -1260,12 +2154,17 @@ union cvmx_sli_msi_w1s_enb1 {
 	struct cvmx_sli_msi_w1s_enb1_s cn66xx;
 	struct cvmx_sli_msi_w1s_enb1_s cn68xx;
 	struct cvmx_sli_msi_w1s_enb1_s cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb1_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1s_enb2 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1s_enb2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t set:64;
+#else
 		uint64_t set:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1s_enb2_s cn61xx;
 	struct cvmx_sli_msi_w1s_enb2_s cn63xx;
@@ -1273,12 +2172,17 @@ union cvmx_sli_msi_w1s_enb2 {
 	struct cvmx_sli_msi_w1s_enb2_s cn66xx;
 	struct cvmx_sli_msi_w1s_enb2_s cn68xx;
 	struct cvmx_sli_msi_w1s_enb2_s cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb2_s cnf71xx;
 };
 
 union cvmx_sli_msi_w1s_enb3 {
 	uint64_t u64;
 	struct cvmx_sli_msi_w1s_enb3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t set:64;
+#else
 		uint64_t set:64;
+#endif
 	} s;
 	struct cvmx_sli_msi_w1s_enb3_s cn61xx;
 	struct cvmx_sli_msi_w1s_enb3_s cn63xx;
@@ -1286,14 +2190,21 @@ union cvmx_sli_msi_w1s_enb3 {
 	struct cvmx_sli_msi_w1s_enb3_s cn66xx;
 	struct cvmx_sli_msi_w1s_enb3_s cn68xx;
 	struct cvmx_sli_msi_w1s_enb3_s cn68xxp1;
+	struct cvmx_sli_msi_w1s_enb3_s cnf71xx;
 };
 
 union cvmx_sli_msi_wr_map {
 	uint64_t u64;
 	struct cvmx_sli_msi_wr_map_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_16_63:48;
 		uint64_t ciu_int:8;
 		uint64_t msi_int:8;
+#else
+		uint64_t msi_int:8;
+		uint64_t ciu_int:8;
+		uint64_t reserved_16_63:48;
+#endif
 	} s;
 	struct cvmx_sli_msi_wr_map_s cn61xx;
 	struct cvmx_sli_msi_wr_map_s cn63xx;
@@ -1301,13 +2212,19 @@ union cvmx_sli_msi_wr_map {
 	struct cvmx_sli_msi_wr_map_s cn66xx;
 	struct cvmx_sli_msi_wr_map_s cn68xx;
 	struct cvmx_sli_msi_wr_map_s cn68xxp1;
+	struct cvmx_sli_msi_wr_map_s cnf71xx;
 };
 
 union cvmx_sli_pcie_msi_rcv {
 	uint64_t u64;
 	struct cvmx_sli_pcie_msi_rcv_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_8_63:56;
 		uint64_t intr:8;
+#else
+		uint64_t intr:8;
+		uint64_t reserved_8_63:56;
+#endif
 	} s;
 	struct cvmx_sli_pcie_msi_rcv_s cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_s cn63xx;
@@ -1315,14 +2232,21 @@ union cvmx_sli_pcie_msi_rcv {
 	struct cvmx_sli_pcie_msi_rcv_s cn66xx;
 	struct cvmx_sli_pcie_msi_rcv_s cn68xx;
 	struct cvmx_sli_pcie_msi_rcv_s cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_s cnf71xx;
 };
 
 union cvmx_sli_pcie_msi_rcv_b1 {
 	uint64_t u64;
 	struct cvmx_sli_pcie_msi_rcv_b1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_16_63:48;
 		uint64_t intr:8;
 		uint64_t reserved_0_7:8;
+#else
+		uint64_t reserved_0_7:8;
+		uint64_t intr:8;
+		uint64_t reserved_16_63:48;
+#endif
 	} s;
 	struct cvmx_sli_pcie_msi_rcv_b1_s cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b1_s cn63xx;
@@ -1330,14 +2254,21 @@ union cvmx_sli_pcie_msi_rcv_b1 {
 	struct cvmx_sli_pcie_msi_rcv_b1_s cn66xx;
 	struct cvmx_sli_pcie_msi_rcv_b1_s cn68xx;
 	struct cvmx_sli_pcie_msi_rcv_b1_s cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b1_s cnf71xx;
 };
 
 union cvmx_sli_pcie_msi_rcv_b2 {
 	uint64_t u64;
 	struct cvmx_sli_pcie_msi_rcv_b2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_24_63:40;
 		uint64_t intr:8;
 		uint64_t reserved_0_15:16;
+#else
+		uint64_t reserved_0_15:16;
+		uint64_t intr:8;
+		uint64_t reserved_24_63:40;
+#endif
 	} s;
 	struct cvmx_sli_pcie_msi_rcv_b2_s cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b2_s cn63xx;
@@ -1345,14 +2276,21 @@ union cvmx_sli_pcie_msi_rcv_b2 {
 	struct cvmx_sli_pcie_msi_rcv_b2_s cn66xx;
 	struct cvmx_sli_pcie_msi_rcv_b2_s cn68xx;
 	struct cvmx_sli_pcie_msi_rcv_b2_s cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b2_s cnf71xx;
 };
 
 union cvmx_sli_pcie_msi_rcv_b3 {
 	uint64_t u64;
 	struct cvmx_sli_pcie_msi_rcv_b3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t intr:8;
 		uint64_t reserved_0_23:24;
+#else
+		uint64_t reserved_0_23:24;
+		uint64_t intr:8;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pcie_msi_rcv_b3_s cn61xx;
 	struct cvmx_sli_pcie_msi_rcv_b3_s cn63xx;
@@ -1360,14 +2298,21 @@ union cvmx_sli_pcie_msi_rcv_b3 {
 	struct cvmx_sli_pcie_msi_rcv_b3_s cn66xx;
 	struct cvmx_sli_pcie_msi_rcv_b3_s cn68xx;
 	struct cvmx_sli_pcie_msi_rcv_b3_s cn68xxp1;
+	struct cvmx_sli_pcie_msi_rcv_b3_s cnf71xx;
 };
 
 union cvmx_sli_pktx_cnts {
 	uint64_t u64;
 	struct cvmx_sli_pktx_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_54_63:10;
 		uint64_t timer:22;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t timer:22;
+		uint64_t reserved_54_63:10;
+#endif
 	} s;
 	struct cvmx_sli_pktx_cnts_s cn61xx;
 	struct cvmx_sli_pktx_cnts_s cn63xx;
@@ -1375,25 +2320,37 @@ union cvmx_sli_pktx_cnts {
 	struct cvmx_sli_pktx_cnts_s cn66xx;
 	struct cvmx_sli_pktx_cnts_s cn68xx;
 	struct cvmx_sli_pktx_cnts_s cn68xxp1;
+	struct cvmx_sli_pktx_cnts_s cnf71xx;
 };
 
 union cvmx_sli_pktx_in_bp {
 	uint64_t u64;
 	struct cvmx_sli_pktx_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t wmark:32;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t wmark:32;
+#endif
 	} s;
 	struct cvmx_sli_pktx_in_bp_s cn61xx;
 	struct cvmx_sli_pktx_in_bp_s cn63xx;
 	struct cvmx_sli_pktx_in_bp_s cn63xxp1;
 	struct cvmx_sli_pktx_in_bp_s cn66xx;
+	struct cvmx_sli_pktx_in_bp_s cnf71xx;
 };
 
 union cvmx_sli_pktx_instr_baddr {
 	uint64_t u64;
 	struct cvmx_sli_pktx_instr_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t addr:61;
 		uint64_t reserved_0_2:3;
+#else
+		uint64_t reserved_0_2:3;
+		uint64_t addr:61;
+#endif
 	} s;
 	struct cvmx_sli_pktx_instr_baddr_s cn61xx;
 	struct cvmx_sli_pktx_instr_baddr_s cn63xx;
@@ -1401,13 +2358,19 @@ union cvmx_sli_pktx_instr_baddr {
 	struct cvmx_sli_pktx_instr_baddr_s cn66xx;
 	struct cvmx_sli_pktx_instr_baddr_s cn68xx;
 	struct cvmx_sli_pktx_instr_baddr_s cn68xxp1;
+	struct cvmx_sli_pktx_instr_baddr_s cnf71xx;
 };
 
 union cvmx_sli_pktx_instr_baoff_dbell {
 	uint64_t u64;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t aoff:32;
 		uint64_t dbell:32;
+#else
+		uint64_t dbell:32;
+		uint64_t aoff:32;
+#endif
 	} s;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn61xx;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn63xx;
@@ -1415,16 +2378,25 @@ union cvmx_sli_pktx_instr_baoff_dbell {
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn66xx;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xx;
 	struct cvmx_sli_pktx_instr_baoff_dbell_s cn68xxp1;
+	struct cvmx_sli_pktx_instr_baoff_dbell_s cnf71xx;
 };
 
 union cvmx_sli_pktx_instr_fifo_rsize {
 	uint64_t u64;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t max:9;
 		uint64_t rrp:9;
 		uint64_t wrp:9;
 		uint64_t fcnt:5;
 		uint64_t rsize:32;
+#else
+		uint64_t rsize:32;
+		uint64_t fcnt:5;
+		uint64_t wrp:9;
+		uint64_t rrp:9;
+		uint64_t max:9;
+#endif
 	} s;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn61xx;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn63xx;
@@ -1432,11 +2404,13 @@ union cvmx_sli_pktx_instr_fifo_rsize {
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn66xx;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xx;
 	struct cvmx_sli_pktx_instr_fifo_rsize_s cn68xxp1;
+	struct cvmx_sli_pktx_instr_fifo_rsize_s cnf71xx;
 };
 
 union cvmx_sli_pktx_instr_header {
 	uint64_t u64;
 	struct cvmx_sli_pktx_instr_header_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_44_63:20;
 		uint64_t pbp:1;
 		uint64_t reserved_38_42:5;
@@ -1458,8 +2432,32 @@ union cvmx_sli_pktx_instr_header {
 		uint64_t ngrp:1;
 		uint64_t ntt:1;
 		uint64_t ntag:1;
+#else
+		uint64_t ntag:1;
+		uint64_t ntt:1;
+		uint64_t ngrp:1;
+		uint64_t nqos:1;
+		uint64_t ngrpext:2;
+		uint64_t skp_len:7;
+		uint64_t reserved_13_13:1;
+		uint64_t par_mode:2;
+		uint64_t reserved_16_20:5;
+		uint64_t use_ihdr:1;
+		uint64_t rntag:1;
+		uint64_t rntt:1;
+		uint64_t rngrp:1;
+		uint64_t rnqos:1;
+		uint64_t rngrpext:2;
+		uint64_t rskp_len:7;
+		uint64_t reserved_35_35:1;
+		uint64_t rparmode:2;
+		uint64_t reserved_38_42:5;
+		uint64_t pbp:1;
+		uint64_t reserved_44_63:20;
+#endif
 	} s;
 	struct cvmx_sli_pktx_instr_header_cn61xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_44_63:20;
 		uint64_t pbp:1;
 		uint64_t reserved_38_42:5;
@@ -1481,20 +2479,50 @@ union cvmx_sli_pktx_instr_header {
 		uint64_t ngrp:1;
 		uint64_t ntt:1;
 		uint64_t ntag:1;
+#else
+		uint64_t ntag:1;
+		uint64_t ntt:1;
+		uint64_t ngrp:1;
+		uint64_t nqos:1;
+		uint64_t reserved_4_5:2;
+		uint64_t skp_len:7;
+		uint64_t reserved_13_13:1;
+		uint64_t par_mode:2;
+		uint64_t reserved_16_20:5;
+		uint64_t use_ihdr:1;
+		uint64_t rntag:1;
+		uint64_t rntt:1;
+		uint64_t rngrp:1;
+		uint64_t rnqos:1;
+		uint64_t reserved_26_27:2;
+		uint64_t rskp_len:7;
+		uint64_t reserved_35_35:1;
+		uint64_t rparmode:2;
+		uint64_t reserved_38_42:5;
+		uint64_t pbp:1;
+		uint64_t reserved_44_63:20;
+#endif
 	} cn61xx;
 	struct cvmx_sli_pktx_instr_header_cn61xx cn63xx;
 	struct cvmx_sli_pktx_instr_header_cn61xx cn63xxp1;
 	struct cvmx_sli_pktx_instr_header_cn61xx cn66xx;
 	struct cvmx_sli_pktx_instr_header_s cn68xx;
 	struct cvmx_sli_pktx_instr_header_cn61xx cn68xxp1;
+	struct cvmx_sli_pktx_instr_header_cn61xx cnf71xx;
 };
 
 union cvmx_sli_pktx_out_size {
 	uint64_t u64;
 	struct cvmx_sli_pktx_out_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_23_63:41;
 		uint64_t isize:7;
 		uint64_t bsize:16;
+#else
+		uint64_t bsize:16;
+		uint64_t isize:7;
+		uint64_t reserved_23_63:41;
+#endif
 	} s;
 	struct cvmx_sli_pktx_out_size_s cn61xx;
 	struct cvmx_sli_pktx_out_size_s cn63xx;
@@ -1502,13 +2530,19 @@ union cvmx_sli_pktx_out_size {
 	struct cvmx_sli_pktx_out_size_s cn66xx;
 	struct cvmx_sli_pktx_out_size_s cn68xx;
 	struct cvmx_sli_pktx_out_size_s cn68xxp1;
+	struct cvmx_sli_pktx_out_size_s cnf71xx;
 };
 
 union cvmx_sli_pktx_slist_baddr {
 	uint64_t u64;
 	struct cvmx_sli_pktx_slist_baddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t addr:60;
 		uint64_t reserved_0_3:4;
+#else
+		uint64_t reserved_0_3:4;
+		uint64_t addr:60;
+#endif
 	} s;
 	struct cvmx_sli_pktx_slist_baddr_s cn61xx;
 	struct cvmx_sli_pktx_slist_baddr_s cn63xx;
@@ -1516,13 +2550,19 @@ union cvmx_sli_pktx_slist_baddr {
 	struct cvmx_sli_pktx_slist_baddr_s cn66xx;
 	struct cvmx_sli_pktx_slist_baddr_s cn68xx;
 	struct cvmx_sli_pktx_slist_baddr_s cn68xxp1;
+	struct cvmx_sli_pktx_slist_baddr_s cnf71xx;
 };
 
 union cvmx_sli_pktx_slist_baoff_dbell {
 	uint64_t u64;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t aoff:32;
 		uint64_t dbell:32;
+#else
+		uint64_t dbell:32;
+		uint64_t aoff:32;
+#endif
 	} s;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn61xx;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn63xx;
@@ -1530,13 +2570,19 @@ union cvmx_sli_pktx_slist_baoff_dbell {
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn66xx;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xx;
 	struct cvmx_sli_pktx_slist_baoff_dbell_s cn68xxp1;
+	struct cvmx_sli_pktx_slist_baoff_dbell_s cnf71xx;
 };
 
 union cvmx_sli_pktx_slist_fifo_rsize {
 	uint64_t u64;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t rsize:32;
+#else
+		uint64_t rsize:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn61xx;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn63xx;
@@ -1544,13 +2590,19 @@ union cvmx_sli_pktx_slist_fifo_rsize {
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn66xx;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xx;
 	struct cvmx_sli_pktx_slist_fifo_rsize_s cn68xxp1;
+	struct cvmx_sli_pktx_slist_fifo_rsize_s cnf71xx;
 };
 
 union cvmx_sli_pkt_cnt_int {
 	uint64_t u64;
 	struct cvmx_sli_pkt_cnt_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t port:32;
+#else
+		uint64_t port:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_cnt_int_s cn61xx;
 	struct cvmx_sli_pkt_cnt_int_s cn63xx;
@@ -1558,13 +2610,19 @@ union cvmx_sli_pkt_cnt_int {
 	struct cvmx_sli_pkt_cnt_int_s cn66xx;
 	struct cvmx_sli_pkt_cnt_int_s cn68xx;
 	struct cvmx_sli_pkt_cnt_int_s cn68xxp1;
+	struct cvmx_sli_pkt_cnt_int_s cnf71xx;
 };
 
 union cvmx_sli_pkt_cnt_int_enb {
 	uint64_t u64;
 	struct cvmx_sli_pkt_cnt_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t port:32;
+#else
+		uint64_t port:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_cnt_int_enb_s cn61xx;
 	struct cvmx_sli_pkt_cnt_int_enb_s cn63xx;
@@ -1572,14 +2630,21 @@ union cvmx_sli_pkt_cnt_int_enb {
 	struct cvmx_sli_pkt_cnt_int_enb_s cn66xx;
 	struct cvmx_sli_pkt_cnt_int_enb_s cn68xx;
 	struct cvmx_sli_pkt_cnt_int_enb_s cn68xxp1;
+	struct cvmx_sli_pkt_cnt_int_enb_s cnf71xx;
 };
 
 union cvmx_sli_pkt_ctl {
 	uint64_t u64;
 	struct cvmx_sli_pkt_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_5_63:59;
 		uint64_t ring_en:1;
 		uint64_t pkt_bp:4;
+#else
+		uint64_t pkt_bp:4;
+		uint64_t ring_en:1;
+		uint64_t reserved_5_63:59;
+#endif
 	} s;
 	struct cvmx_sli_pkt_ctl_s cn61xx;
 	struct cvmx_sli_pkt_ctl_s cn63xx;
@@ -1587,12 +2652,17 @@ union cvmx_sli_pkt_ctl {
 	struct cvmx_sli_pkt_ctl_s cn66xx;
 	struct cvmx_sli_pkt_ctl_s cn68xx;
 	struct cvmx_sli_pkt_ctl_s cn68xxp1;
+	struct cvmx_sli_pkt_ctl_s cnf71xx;
 };
 
 union cvmx_sli_pkt_data_out_es {
 	uint64_t u64;
 	struct cvmx_sli_pkt_data_out_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t es:64;
+#else
 		uint64_t es:64;
+#endif
 	} s;
 	struct cvmx_sli_pkt_data_out_es_s cn61xx;
 	struct cvmx_sli_pkt_data_out_es_s cn63xx;
@@ -1600,13 +2670,19 @@ union cvmx_sli_pkt_data_out_es {
 	struct cvmx_sli_pkt_data_out_es_s cn66xx;
 	struct cvmx_sli_pkt_data_out_es_s cn68xx;
 	struct cvmx_sli_pkt_data_out_es_s cn68xxp1;
+	struct cvmx_sli_pkt_data_out_es_s cnf71xx;
 };
 
 union cvmx_sli_pkt_data_out_ns {
 	uint64_t u64;
 	struct cvmx_sli_pkt_data_out_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t nsr:32;
+#else
+		uint64_t nsr:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_data_out_ns_s cn61xx;
 	struct cvmx_sli_pkt_data_out_ns_s cn63xx;
@@ -1614,13 +2690,19 @@ union cvmx_sli_pkt_data_out_ns {
 	struct cvmx_sli_pkt_data_out_ns_s cn66xx;
 	struct cvmx_sli_pkt_data_out_ns_s cn68xx;
 	struct cvmx_sli_pkt_data_out_ns_s cn68xxp1;
+	struct cvmx_sli_pkt_data_out_ns_s cnf71xx;
 };
 
 union cvmx_sli_pkt_data_out_ror {
 	uint64_t u64;
 	struct cvmx_sli_pkt_data_out_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t ror:32;
+#else
+		uint64_t ror:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_data_out_ror_s cn61xx;
 	struct cvmx_sli_pkt_data_out_ror_s cn63xx;
@@ -1628,13 +2710,19 @@ union cvmx_sli_pkt_data_out_ror {
 	struct cvmx_sli_pkt_data_out_ror_s cn66xx;
 	struct cvmx_sli_pkt_data_out_ror_s cn68xx;
 	struct cvmx_sli_pkt_data_out_ror_s cn68xxp1;
+	struct cvmx_sli_pkt_data_out_ror_s cnf71xx;
 };
 
 union cvmx_sli_pkt_dpaddr {
 	uint64_t u64;
 	struct cvmx_sli_pkt_dpaddr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t dptr:32;
+#else
+		uint64_t dptr:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_dpaddr_s cn61xx;
 	struct cvmx_sli_pkt_dpaddr_s cn63xx;
@@ -1642,25 +2730,37 @@ union cvmx_sli_pkt_dpaddr {
 	struct cvmx_sli_pkt_dpaddr_s cn66xx;
 	struct cvmx_sli_pkt_dpaddr_s cn68xx;
 	struct cvmx_sli_pkt_dpaddr_s cn68xxp1;
+	struct cvmx_sli_pkt_dpaddr_s cnf71xx;
 };
 
 union cvmx_sli_pkt_in_bp {
 	uint64_t u64;
 	struct cvmx_sli_pkt_in_bp_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t bp:32;
+#else
+		uint64_t bp:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_in_bp_s cn61xx;
 	struct cvmx_sli_pkt_in_bp_s cn63xx;
 	struct cvmx_sli_pkt_in_bp_s cn63xxp1;
 	struct cvmx_sli_pkt_in_bp_s cn66xx;
+	struct cvmx_sli_pkt_in_bp_s cnf71xx;
 };
 
 union cvmx_sli_pkt_in_donex_cnts {
 	uint64_t u64;
 	struct cvmx_sli_pkt_in_donex_cnts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_in_donex_cnts_s cn61xx;
 	struct cvmx_sli_pkt_in_donex_cnts_s cn63xx;
@@ -1668,13 +2768,19 @@ union cvmx_sli_pkt_in_donex_cnts {
 	struct cvmx_sli_pkt_in_donex_cnts_s cn66xx;
 	struct cvmx_sli_pkt_in_donex_cnts_s cn68xx;
 	struct cvmx_sli_pkt_in_donex_cnts_s cn68xxp1;
+	struct cvmx_sli_pkt_in_donex_cnts_s cnf71xx;
 };
 
 union cvmx_sli_pkt_in_instr_counts {
 	uint64_t u64;
 	struct cvmx_sli_pkt_in_instr_counts_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t wr_cnt:32;
 		uint64_t rd_cnt:32;
+#else
+		uint64_t rd_cnt:32;
+		uint64_t wr_cnt:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_in_instr_counts_s cn61xx;
 	struct cvmx_sli_pkt_in_instr_counts_s cn63xx;
@@ -1682,12 +2788,17 @@ union cvmx_sli_pkt_in_instr_counts {
 	struct cvmx_sli_pkt_in_instr_counts_s cn66xx;
 	struct cvmx_sli_pkt_in_instr_counts_s cn68xx;
 	struct cvmx_sli_pkt_in_instr_counts_s cn68xxp1;
+	struct cvmx_sli_pkt_in_instr_counts_s cnf71xx;
 };
 
 union cvmx_sli_pkt_in_pcie_port {
 	uint64_t u64;
 	struct cvmx_sli_pkt_in_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t pp:64;
+#else
 		uint64_t pp:64;
+#endif
 	} s;
 	struct cvmx_sli_pkt_in_pcie_port_s cn61xx;
 	struct cvmx_sli_pkt_in_pcie_port_s cn63xx;
@@ -1695,11 +2806,13 @@ union cvmx_sli_pkt_in_pcie_port {
 	struct cvmx_sli_pkt_in_pcie_port_s cn66xx;
 	struct cvmx_sli_pkt_in_pcie_port_s cn68xx;
 	struct cvmx_sli_pkt_in_pcie_port_s cn68xxp1;
+	struct cvmx_sli_pkt_in_pcie_port_s cnf71xx;
 };
 
 union cvmx_sli_pkt_input_control {
 	uint64_t u64;
 	struct cvmx_sli_pkt_input_control_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t prd_erst:1;
 		uint64_t prd_rds:7;
 		uint64_t gii_erst:1;
@@ -1717,9 +2830,29 @@ union cvmx_sli_pkt_input_control {
 		uint64_t nsr:1;
 		uint64_t esr:2;
 		uint64_t ror:1;
+#else
+		uint64_t ror:1;
+		uint64_t esr:2;
+		uint64_t nsr:1;
+		uint64_t use_csr:1;
+		uint64_t d_ror:1;
+		uint64_t d_esr:2;
+		uint64_t d_nsr:1;
+		uint64_t pbp_dhi:13;
+		uint64_t pkt_rr:1;
+		uint64_t pin_rst:1;
+		uint64_t reserved_24_39:16;
+		uint64_t prc_idle:1;
+		uint64_t reserved_41_47:7;
+		uint64_t gii_rds:7;
+		uint64_t gii_erst:1;
+		uint64_t prd_rds:7;
+		uint64_t prd_erst:1;
+#endif
 	} s;
 	struct cvmx_sli_pkt_input_control_s cn61xx;
 	struct cvmx_sli_pkt_input_control_cn63xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_23_63:41;
 		uint64_t pkt_rr:1;
 		uint64_t pbp_dhi:13;
@@ -1730,18 +2863,36 @@ union cvmx_sli_pkt_input_control {
 		uint64_t nsr:1;
 		uint64_t esr:2;
 		uint64_t ror:1;
+#else
+		uint64_t ror:1;
+		uint64_t esr:2;
+		uint64_t nsr:1;
+		uint64_t use_csr:1;
+		uint64_t d_ror:1;
+		uint64_t d_esr:2;
+		uint64_t d_nsr:1;
+		uint64_t pbp_dhi:13;
+		uint64_t pkt_rr:1;
+		uint64_t reserved_23_63:41;
+#endif
 	} cn63xx;
 	struct cvmx_sli_pkt_input_control_cn63xx cn63xxp1;
 	struct cvmx_sli_pkt_input_control_s cn66xx;
 	struct cvmx_sli_pkt_input_control_s cn68xx;
 	struct cvmx_sli_pkt_input_control_s cn68xxp1;
+	struct cvmx_sli_pkt_input_control_s cnf71xx;
 };
 
 union cvmx_sli_pkt_instr_enb {
 	uint64_t u64;
 	struct cvmx_sli_pkt_instr_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t enb:32;
+#else
+		uint64_t enb:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_instr_enb_s cn61xx;
 	struct cvmx_sli_pkt_instr_enb_s cn63xx;
@@ -1749,12 +2900,17 @@ union cvmx_sli_pkt_instr_enb {
 	struct cvmx_sli_pkt_instr_enb_s cn66xx;
 	struct cvmx_sli_pkt_instr_enb_s cn68xx;
 	struct cvmx_sli_pkt_instr_enb_s cn68xxp1;
+	struct cvmx_sli_pkt_instr_enb_s cnf71xx;
 };
 
 union cvmx_sli_pkt_instr_rd_size {
 	uint64_t u64;
 	struct cvmx_sli_pkt_instr_rd_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t rdsize:64;
+#else
 		uint64_t rdsize:64;
+#endif
 	} s;
 	struct cvmx_sli_pkt_instr_rd_size_s cn61xx;
 	struct cvmx_sli_pkt_instr_rd_size_s cn63xx;
@@ -1762,13 +2918,19 @@ union cvmx_sli_pkt_instr_rd_size {
 	struct cvmx_sli_pkt_instr_rd_size_s cn66xx;
 	struct cvmx_sli_pkt_instr_rd_size_s cn68xx;
 	struct cvmx_sli_pkt_instr_rd_size_s cn68xxp1;
+	struct cvmx_sli_pkt_instr_rd_size_s cnf71xx;
 };
 
 union cvmx_sli_pkt_instr_size {
 	uint64_t u64;
 	struct cvmx_sli_pkt_instr_size_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t is_64b:32;
+#else
+		uint64_t is_64b:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_instr_size_s cn61xx;
 	struct cvmx_sli_pkt_instr_size_s cn63xx;
@@ -1776,14 +2938,21 @@ union cvmx_sli_pkt_instr_size {
 	struct cvmx_sli_pkt_instr_size_s cn66xx;
 	struct cvmx_sli_pkt_instr_size_s cn68xx;
 	struct cvmx_sli_pkt_instr_size_s cn68xxp1;
+	struct cvmx_sli_pkt_instr_size_s cnf71xx;
 };
 
 union cvmx_sli_pkt_int_levels {
 	uint64_t u64;
 	struct cvmx_sli_pkt_int_levels_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_54_63:10;
 		uint64_t time:22;
 		uint64_t cnt:32;
+#else
+		uint64_t cnt:32;
+		uint64_t time:22;
+		uint64_t reserved_54_63:10;
+#endif
 	} s;
 	struct cvmx_sli_pkt_int_levels_s cn61xx;
 	struct cvmx_sli_pkt_int_levels_s cn63xx;
@@ -1791,13 +2960,19 @@ union cvmx_sli_pkt_int_levels {
 	struct cvmx_sli_pkt_int_levels_s cn66xx;
 	struct cvmx_sli_pkt_int_levels_s cn68xx;
 	struct cvmx_sli_pkt_int_levels_s cn68xxp1;
+	struct cvmx_sli_pkt_int_levels_s cnf71xx;
 };
 
 union cvmx_sli_pkt_iptr {
 	uint64_t u64;
 	struct cvmx_sli_pkt_iptr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t iptr:32;
+#else
+		uint64_t iptr:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_iptr_s cn61xx;
 	struct cvmx_sli_pkt_iptr_s cn63xx;
@@ -1805,13 +2980,19 @@ union cvmx_sli_pkt_iptr {
 	struct cvmx_sli_pkt_iptr_s cn66xx;
 	struct cvmx_sli_pkt_iptr_s cn68xx;
 	struct cvmx_sli_pkt_iptr_s cn68xxp1;
+	struct cvmx_sli_pkt_iptr_s cnf71xx;
 };
 
 union cvmx_sli_pkt_out_bmode {
 	uint64_t u64;
 	struct cvmx_sli_pkt_out_bmode_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t bmode:32;
+#else
+		uint64_t bmode:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_out_bmode_s cn61xx;
 	struct cvmx_sli_pkt_out_bmode_s cn63xx;
@@ -1819,13 +3000,19 @@ union cvmx_sli_pkt_out_bmode {
 	struct cvmx_sli_pkt_out_bmode_s cn66xx;
 	struct cvmx_sli_pkt_out_bmode_s cn68xx;
 	struct cvmx_sli_pkt_out_bmode_s cn68xxp1;
+	struct cvmx_sli_pkt_out_bmode_s cnf71xx;
 };
 
 union cvmx_sli_pkt_out_bp_en {
 	uint64_t u64;
 	struct cvmx_sli_pkt_out_bp_en_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t bp_en:32;
+#else
+		uint64_t bp_en:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_out_bp_en_s cn68xx;
 	struct cvmx_sli_pkt_out_bp_en_s cn68xxp1;
@@ -1834,8 +3021,13 @@ union cvmx_sli_pkt_out_bp_en {
 union cvmx_sli_pkt_out_enb {
 	uint64_t u64;
 	struct cvmx_sli_pkt_out_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t enb:32;
+#else
+		uint64_t enb:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_out_enb_s cn61xx;
 	struct cvmx_sli_pkt_out_enb_s cn63xx;
@@ -1843,13 +3035,19 @@ union cvmx_sli_pkt_out_enb {
 	struct cvmx_sli_pkt_out_enb_s cn66xx;
 	struct cvmx_sli_pkt_out_enb_s cn68xx;
 	struct cvmx_sli_pkt_out_enb_s cn68xxp1;
+	struct cvmx_sli_pkt_out_enb_s cnf71xx;
 };
 
 union cvmx_sli_pkt_output_wmark {
 	uint64_t u64;
 	struct cvmx_sli_pkt_output_wmark_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t wmark:32;
+#else
+		uint64_t wmark:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_output_wmark_s cn61xx;
 	struct cvmx_sli_pkt_output_wmark_s cn63xx;
@@ -1857,12 +3055,17 @@ union cvmx_sli_pkt_output_wmark {
 	struct cvmx_sli_pkt_output_wmark_s cn66xx;
 	struct cvmx_sli_pkt_output_wmark_s cn68xx;
 	struct cvmx_sli_pkt_output_wmark_s cn68xxp1;
+	struct cvmx_sli_pkt_output_wmark_s cnf71xx;
 };
 
 union cvmx_sli_pkt_pcie_port {
 	uint64_t u64;
 	struct cvmx_sli_pkt_pcie_port_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t pp:64;
+#else
 		uint64_t pp:64;
+#endif
 	} s;
 	struct cvmx_sli_pkt_pcie_port_s cn61xx;
 	struct cvmx_sli_pkt_pcie_port_s cn63xx;
@@ -1870,13 +3073,19 @@ union cvmx_sli_pkt_pcie_port {
 	struct cvmx_sli_pkt_pcie_port_s cn66xx;
 	struct cvmx_sli_pkt_pcie_port_s cn68xx;
 	struct cvmx_sli_pkt_pcie_port_s cn68xxp1;
+	struct cvmx_sli_pkt_pcie_port_s cnf71xx;
 };
 
 union cvmx_sli_pkt_port_in_rst {
 	uint64_t u64;
 	struct cvmx_sli_pkt_port_in_rst_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t in_rst:32;
 		uint64_t out_rst:32;
+#else
+		uint64_t out_rst:32;
+		uint64_t in_rst:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_port_in_rst_s cn61xx;
 	struct cvmx_sli_pkt_port_in_rst_s cn63xx;
@@ -1884,12 +3093,17 @@ union cvmx_sli_pkt_port_in_rst {
 	struct cvmx_sli_pkt_port_in_rst_s cn66xx;
 	struct cvmx_sli_pkt_port_in_rst_s cn68xx;
 	struct cvmx_sli_pkt_port_in_rst_s cn68xxp1;
+	struct cvmx_sli_pkt_port_in_rst_s cnf71xx;
 };
 
 union cvmx_sli_pkt_slist_es {
 	uint64_t u64;
 	struct cvmx_sli_pkt_slist_es_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t es:64;
+#else
+		uint64_t es:64;
+#endif
 	} s;
 	struct cvmx_sli_pkt_slist_es_s cn61xx;
 	struct cvmx_sli_pkt_slist_es_s cn63xx;
@@ -1897,13 +3111,19 @@ union cvmx_sli_pkt_slist_es {
 	struct cvmx_sli_pkt_slist_es_s cn66xx;
 	struct cvmx_sli_pkt_slist_es_s cn68xx;
 	struct cvmx_sli_pkt_slist_es_s cn68xxp1;
+	struct cvmx_sli_pkt_slist_es_s cnf71xx;
 };
 
 union cvmx_sli_pkt_slist_ns {
 	uint64_t u64;
 	struct cvmx_sli_pkt_slist_ns_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t nsr:32;
+#else
+		uint64_t nsr:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_slist_ns_s cn61xx;
 	struct cvmx_sli_pkt_slist_ns_s cn63xx;
@@ -1911,13 +3131,19 @@ union cvmx_sli_pkt_slist_ns {
 	struct cvmx_sli_pkt_slist_ns_s cn66xx;
 	struct cvmx_sli_pkt_slist_ns_s cn68xx;
 	struct cvmx_sli_pkt_slist_ns_s cn68xxp1;
+	struct cvmx_sli_pkt_slist_ns_s cnf71xx;
 };
 
 union cvmx_sli_pkt_slist_ror {
 	uint64_t u64;
 	struct cvmx_sli_pkt_slist_ror_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t ror:32;
+#else
+		uint64_t ror:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_slist_ror_s cn61xx;
 	struct cvmx_sli_pkt_slist_ror_s cn63xx;
@@ -1925,13 +3151,19 @@ union cvmx_sli_pkt_slist_ror {
 	struct cvmx_sli_pkt_slist_ror_s cn66xx;
 	struct cvmx_sli_pkt_slist_ror_s cn68xx;
 	struct cvmx_sli_pkt_slist_ror_s cn68xxp1;
+	struct cvmx_sli_pkt_slist_ror_s cnf71xx;
 };
 
 union cvmx_sli_pkt_time_int {
 	uint64_t u64;
 	struct cvmx_sli_pkt_time_int_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t port:32;
+#else
+		uint64_t port:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_time_int_s cn61xx;
 	struct cvmx_sli_pkt_time_int_s cn63xx;
@@ -1939,13 +3171,19 @@ union cvmx_sli_pkt_time_int {
 	struct cvmx_sli_pkt_time_int_s cn66xx;
 	struct cvmx_sli_pkt_time_int_s cn68xx;
 	struct cvmx_sli_pkt_time_int_s cn68xxp1;
+	struct cvmx_sli_pkt_time_int_s cnf71xx;
 };
 
 union cvmx_sli_pkt_time_int_enb {
 	uint64_t u64;
 	struct cvmx_sli_pkt_time_int_enb_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t port:32;
+#else
+		uint64_t port:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_pkt_time_int_enb_s cn61xx;
 	struct cvmx_sli_pkt_time_int_enb_s cn63xx;
@@ -1953,11 +3191,13 @@ union cvmx_sli_pkt_time_int_enb {
 	struct cvmx_sli_pkt_time_int_enb_s cn66xx;
 	struct cvmx_sli_pkt_time_int_enb_s cn68xx;
 	struct cvmx_sli_pkt_time_int_enb_s cn68xxp1;
+	struct cvmx_sli_pkt_time_int_enb_s cnf71xx;
 };
 
 union cvmx_sli_portx_pkind {
 	uint64_t u64;
 	struct cvmx_sli_portx_pkind_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_25_63:39;
 		uint64_t rpk_enb:1;
 		uint64_t reserved_22_23:2;
@@ -1966,23 +3206,47 @@ union cvmx_sli_portx_pkind {
 		uint64_t bpkind:6;
 		uint64_t reserved_6_7:2;
 		uint64_t pkind:6;
+#else
+		uint64_t pkind:6;
+		uint64_t reserved_6_7:2;
+		uint64_t bpkind:6;
+		uint64_t reserved_14_15:2;
+		uint64_t pkindr:6;
+		uint64_t reserved_22_23:2;
+		uint64_t rpk_enb:1;
+		uint64_t reserved_25_63:39;
+#endif
 	} s;
 	struct cvmx_sli_portx_pkind_s cn68xx;
 	struct cvmx_sli_portx_pkind_cn68xxp1 {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_14_63:50;
 		uint64_t bpkind:6;
 		uint64_t reserved_6_7:2;
 		uint64_t pkind:6;
+#else
+		uint64_t pkind:6;
+		uint64_t reserved_6_7:2;
+		uint64_t bpkind:6;
+		uint64_t reserved_14_63:50;
+#endif
 	} cn68xxp1;
 };
 
 union cvmx_sli_s2m_portx_ctl {
 	uint64_t u64;
 	struct cvmx_sli_s2m_portx_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_5_63:59;
 		uint64_t wind_d:1;
 		uint64_t bar0_d:1;
 		uint64_t mrrs:3;
+#else
+		uint64_t mrrs:3;
+		uint64_t bar0_d:1;
+		uint64_t wind_d:1;
+		uint64_t reserved_5_63:59;
+#endif
 	} s;
 	struct cvmx_sli_s2m_portx_ctl_s cn61xx;
 	struct cvmx_sli_s2m_portx_ctl_s cn63xx;
@@ -1990,12 +3254,17 @@ union cvmx_sli_s2m_portx_ctl {
 	struct cvmx_sli_s2m_portx_ctl_s cn66xx;
 	struct cvmx_sli_s2m_portx_ctl_s cn68xx;
 	struct cvmx_sli_s2m_portx_ctl_s cn68xxp1;
+	struct cvmx_sli_s2m_portx_ctl_s cnf71xx;
 };
 
 union cvmx_sli_scratch_1 {
 	uint64_t u64;
 	struct cvmx_sli_scratch_1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_scratch_1_s cn61xx;
 	struct cvmx_sli_scratch_1_s cn63xx;
@@ -2003,12 +3272,17 @@ union cvmx_sli_scratch_1 {
 	struct cvmx_sli_scratch_1_s cn66xx;
 	struct cvmx_sli_scratch_1_s cn68xx;
 	struct cvmx_sli_scratch_1_s cn68xxp1;
+	struct cvmx_sli_scratch_1_s cnf71xx;
 };
 
 union cvmx_sli_scratch_2 {
 	uint64_t u64;
 	struct cvmx_sli_scratch_2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t data:64;
+#else
 		uint64_t data:64;
+#endif
 	} s;
 	struct cvmx_sli_scratch_2_s cn61xx;
 	struct cvmx_sli_scratch_2_s cn63xx;
@@ -2016,15 +3290,23 @@ union cvmx_sli_scratch_2 {
 	struct cvmx_sli_scratch_2_s cn66xx;
 	struct cvmx_sli_scratch_2_s cn68xx;
 	struct cvmx_sli_scratch_2_s cn68xxp1;
+	struct cvmx_sli_scratch_2_s cnf71xx;
 };
 
 union cvmx_sli_state1 {
 	uint64_t u64;
 	struct cvmx_sli_state1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t cpl1:12;
 		uint64_t cpl0:12;
 		uint64_t arb:1;
 		uint64_t csr:39;
+#else
+		uint64_t csr:39;
+		uint64_t arb:1;
+		uint64_t cpl0:12;
+		uint64_t cpl1:12;
+#endif
 	} s;
 	struct cvmx_sli_state1_s cn61xx;
 	struct cvmx_sli_state1_s cn63xx;
@@ -2032,11 +3314,13 @@ union cvmx_sli_state1 {
 	struct cvmx_sli_state1_s cn66xx;
 	struct cvmx_sli_state1_s cn68xx;
 	struct cvmx_sli_state1_s cn68xxp1;
+	struct cvmx_sli_state1_s cnf71xx;
 };
 
 union cvmx_sli_state2 {
 	uint64_t u64;
 	struct cvmx_sli_state2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_56_63:8;
 		uint64_t nnp1:8;
 		uint64_t reserved_47_47:1;
@@ -2045,6 +3329,16 @@ union cvmx_sli_state2 {
 		uint64_t csm0:15;
 		uint64_t nnp0:8;
 		uint64_t nnd:8;
+#else
+		uint64_t nnd:8;
+		uint64_t nnp0:8;
+		uint64_t csm0:15;
+		uint64_t csm1:15;
+		uint64_t rac:1;
+		uint64_t reserved_47_47:1;
+		uint64_t nnp1:8;
+		uint64_t reserved_56_63:8;
+#endif
 	} s;
 	struct cvmx_sli_state2_s cn61xx;
 	struct cvmx_sli_state2_s cn63xx;
@@ -2052,16 +3346,25 @@ union cvmx_sli_state2 {
 	struct cvmx_sli_state2_s cn66xx;
 	struct cvmx_sli_state2_s cn68xx;
 	struct cvmx_sli_state2_s cn68xxp1;
+	struct cvmx_sli_state2_s cnf71xx;
 };
 
 union cvmx_sli_state3 {
 	uint64_t u64;
 	struct cvmx_sli_state3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_56_63:8;
 		uint64_t psm1:15;
 		uint64_t psm0:15;
 		uint64_t nsm1:13;
 		uint64_t nsm0:13;
+#else
+		uint64_t nsm0:13;
+		uint64_t nsm1:13;
+		uint64_t psm0:15;
+		uint64_t psm1:15;
+		uint64_t reserved_56_63:8;
+#endif
 	} s;
 	struct cvmx_sli_state3_s cn61xx;
 	struct cvmx_sli_state3_s cn63xx;
@@ -2069,15 +3372,23 @@ union cvmx_sli_state3 {
 	struct cvmx_sli_state3_s cn66xx;
 	struct cvmx_sli_state3_s cn68xx;
 	struct cvmx_sli_state3_s cn68xxp1;
+	struct cvmx_sli_state3_s cnf71xx;
 };
 
 union cvmx_sli_tx_pipe {
 	uint64_t u64;
 	struct cvmx_sli_tx_pipe_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_24_63:40;
 		uint64_t nump:8;
 		uint64_t reserved_7_15:9;
 		uint64_t base:7;
+#else
+		uint64_t base:7;
+		uint64_t reserved_7_15:9;
+		uint64_t nump:8;
+		uint64_t reserved_24_63:40;
+#endif
 	} s;
 	struct cvmx_sli_tx_pipe_s cn68xx;
 	struct cvmx_sli_tx_pipe_s cn68xxp1;
@@ -2086,10 +3397,17 @@ union cvmx_sli_tx_pipe {
 union cvmx_sli_win_rd_addr {
 	uint64_t u64;
 	struct cvmx_sli_win_rd_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_51_63:13;
 		uint64_t ld_cmd:2;
 		uint64_t iobit:1;
 		uint64_t rd_addr:48;
+#else
+		uint64_t rd_addr:48;
+		uint64_t iobit:1;
+		uint64_t ld_cmd:2;
+		uint64_t reserved_51_63:13;
+#endif
 	} s;
 	struct cvmx_sli_win_rd_addr_s cn61xx;
 	struct cvmx_sli_win_rd_addr_s cn63xx;
@@ -2097,12 +3415,17 @@ union cvmx_sli_win_rd_addr {
 	struct cvmx_sli_win_rd_addr_s cn66xx;
 	struct cvmx_sli_win_rd_addr_s cn68xx;
 	struct cvmx_sli_win_rd_addr_s cn68xxp1;
+	struct cvmx_sli_win_rd_addr_s cnf71xx;
 };
 
 union cvmx_sli_win_rd_data {
 	uint64_t u64;
 	struct cvmx_sli_win_rd_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
+		uint64_t rd_data:64;
+#else
 		uint64_t rd_data:64;
+#endif
 	} s;
 	struct cvmx_sli_win_rd_data_s cn61xx;
 	struct cvmx_sli_win_rd_data_s cn63xx;
@@ -2110,15 +3433,23 @@ union cvmx_sli_win_rd_data {
 	struct cvmx_sli_win_rd_data_s cn66xx;
 	struct cvmx_sli_win_rd_data_s cn68xx;
 	struct cvmx_sli_win_rd_data_s cn68xxp1;
+	struct cvmx_sli_win_rd_data_s cnf71xx;
 };
 
 union cvmx_sli_win_wr_addr {
 	uint64_t u64;
 	struct cvmx_sli_win_wr_addr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_49_63:15;
 		uint64_t iobit:1;
 		uint64_t wr_addr:45;
 		uint64_t reserved_0_2:3;
+#else
+		uint64_t reserved_0_2:3;
+		uint64_t wr_addr:45;
+		uint64_t iobit:1;
+		uint64_t reserved_49_63:15;
+#endif
 	} s;
 	struct cvmx_sli_win_wr_addr_s cn61xx;
 	struct cvmx_sli_win_wr_addr_s cn63xx;
@@ -2126,12 +3457,17 @@ union cvmx_sli_win_wr_addr {
 	struct cvmx_sli_win_wr_addr_s cn66xx;
 	struct cvmx_sli_win_wr_addr_s cn68xx;
 	struct cvmx_sli_win_wr_addr_s cn68xxp1;
+	struct cvmx_sli_win_wr_addr_s cnf71xx;
 };
 
 union cvmx_sli_win_wr_data {
 	uint64_t u64;
 	struct cvmx_sli_win_wr_data_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t wr_data:64;
+#else
+		uint64_t wr_data:64;
+#endif
 	} s;
 	struct cvmx_sli_win_wr_data_s cn61xx;
 	struct cvmx_sli_win_wr_data_s cn63xx;
@@ -2139,13 +3475,19 @@ union cvmx_sli_win_wr_data {
 	struct cvmx_sli_win_wr_data_s cn66xx;
 	struct cvmx_sli_win_wr_data_s cn68xx;
 	struct cvmx_sli_win_wr_data_s cn68xxp1;
+	struct cvmx_sli_win_wr_data_s cnf71xx;
 };
 
 union cvmx_sli_win_wr_mask {
 	uint64_t u64;
 	struct cvmx_sli_win_wr_mask_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_8_63:56;
 		uint64_t wr_mask:8;
+#else
+		uint64_t wr_mask:8;
+		uint64_t reserved_8_63:56;
+#endif
 	} s;
 	struct cvmx_sli_win_wr_mask_s cn61xx;
 	struct cvmx_sli_win_wr_mask_s cn63xx;
@@ -2153,13 +3495,19 @@ union cvmx_sli_win_wr_mask {
 	struct cvmx_sli_win_wr_mask_s cn66xx;
 	struct cvmx_sli_win_wr_mask_s cn68xx;
 	struct cvmx_sli_win_wr_mask_s cn68xxp1;
+	struct cvmx_sli_win_wr_mask_s cnf71xx;
 };
 
 union cvmx_sli_window_ctl {
 	uint64_t u64;
 	struct cvmx_sli_window_ctl_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_32_63:32;
 		uint64_t time:32;
+#else
+		uint64_t time:32;
+		uint64_t reserved_32_63:32;
+#endif
 	} s;
 	struct cvmx_sli_window_ctl_s cn61xx;
 	struct cvmx_sli_window_ctl_s cn63xx;
@@ -2167,6 +3515,7 @@ union cvmx_sli_window_ctl {
 	struct cvmx_sli_window_ctl_s cn66xx;
 	struct cvmx_sli_window_ctl_s cn68xx;
 	struct cvmx_sli_window_ctl_s cn68xxp1;
+	struct cvmx_sli_window_ctl_s cnf71xx;
 };
 
 #endif