diff options
| author | David Daney <ddaney@caviumnetworks.com> | 2010-10-07 16:03:40 -0700 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-10-29 19:08:33 +0100 |
| commit | aa32a955ae46d4117e880417c89a2efcc88579c2 (patch) | |
| tree | 538f1564b70d017b224a423d99bc2a0366c1f745 /arch/mips/include/asm/octeon/cvmx-l2t-defs.h | |
| parent | b93b2abce497873be97d765b848e0a955d29f200 (diff) | |
| download | op-kernel-dev-aa32a955ae46d4117e880417c89a2efcc88579c2.zip op-kernel-dev-aa32a955ae46d4117e880417c89a2efcc88579c2.tar.gz | |
MIPS: Octeon: Update register definitions for CN63XX chips
The CN63XX is a new 6-CPU SOC based on the new OCTEON II CPU cores.
Join some lines back together. This makes some of them exceed 80
columns, but they are uninteresting and this unclutters things.
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1668/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/octeon/cvmx-l2t-defs.h')
| -rw-r--r-- | arch/mips/include/asm/octeon/cvmx-l2t-defs.h | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h index 2639a3f..873968f 100644 --- a/arch/mips/include/asm/octeon/cvmx-l2t-defs.h +++ b/arch/mips/include/asm/octeon/cvmx-l2t-defs.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2008 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -28,8 +28,7 @@ #ifndef __CVMX_L2T_DEFS_H__ #define __CVMX_L2T_DEFS_H__ -#define CVMX_L2T_ERR \ - CVMX_ADD_IO_SEG(0x0001180080000008ull) +#define CVMX_L2T_ERR (CVMX_ADD_IO_SEG(0x0001180080000008ull)) union cvmx_l2t_err { uint64_t u64; |
