Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

Pull MIPS update from Ralf Baechle:
 "This is the MIPS update for 3.7.

  A fair chunk of them are platform updates to the Cavium Octeon SOC
  (which involves machine generated header files of considerable size),
  Atheros ATH79xx, RMI aka Netlogic aka Broadcom XLP, Broadcom BCM63xx
  platforms.

  Support for the commercial MIPS simulator MIPSsim has been removed as
  MIPS Technologies is shifting away from this product and Qemu is
  offering various more powerful platforms.  The generic MIPS code can
  now also probe for no-execute / write-only TLB features implemented
  without the full SmartMIPS extension as permitted by the latest MIPS
  processor architecture.  Lots of small changes to generic code."

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (78 commits)
  MIPS: ath79: Fix CPU/DDR frequency calculation for SRIF PLLs
  MIPS: ath79: use correct fractional dividers for {CPU,DDR}_PLL on AR934x
  MIPS: BCM63XX: Properly handle mac address octet overflow
  MIPS: Kconfig: Avoid build errors by hiding USE_OF from the user.
  MIPS: Replace `-' in defconfig filename wth `_' for consistency.
  MIPS: Wire kcmp syscall.
  MIPS: MIPSsim: Remove the MIPSsim platform.
  MIPS: NOTIFY_RESUME is not needed in TIF masks
  MIPS: Merge the identical "return from syscall" per-ABI code
  MIPS: Unobfuscate _TIF..._MASK
  MIPS: Prevent hitting do_notify_resume() with !user_mode(regs).
  MIPS: Replace 'kernel_uses_smartmips_rixi' with 'cpu_has_rixi'.
  MIPS: Add base architecture support for RI and XI.
  MIPS: Optimise TLB handlers for MIPS32/64 R2 cores.
  MIPS: uasm: Add INS and EXT instructions.
  MIPS: Avoid pipeline stalls on some MIPS32R2 cores.
  MIPS: Make VPE count to be one-based.
  MIPS: Add new end of interrupt functionality for GIC.
  MIPS: Add EIC support for GIC.
  MIPS: Code clean-ups for the GIC.
  ...

1 files changed, 170 insertions, 1 deletions

diff --git a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
index 60543e0..11a4562 100644
--- a/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
+++ b/arch/mips/include/asm/octeon/cvmx-l2d-defs.h
@@ -4,7 +4,7 @@
  * Contact: support@caviumnetworks.com
  * This file is part of the OCTEON SDK
  *
- * Copyright (c) 2003-2010 Cavium Networks
+ * Copyright (c) 2003-2012 Cavium Networks
  *
  * This file is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License, Version 2, as
@@ -44,9 +44,15 @@
 union cvmx_l2d_bst0 {
 	uint64_t u64;
 	struct cvmx_l2d_bst0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_35_63:29;
 		uint64_t ftl:1;
 		uint64_t q0stat:34;
+#else
+		uint64_t q0stat:34;
+		uint64_t ftl:1;
+		uint64_t reserved_35_63:29;
+#endif
 	} s;
 	struct cvmx_l2d_bst0_s cn30xx;
 	struct cvmx_l2d_bst0_s cn31xx;
@@ -64,8 +70,13 @@ union cvmx_l2d_bst0 {
 union cvmx_l2d_bst1 {
 	uint64_t u64;
 	struct cvmx_l2d_bst1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q1stat:34;
+#else
+		uint64_t q1stat:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_bst1_s cn30xx;
 	struct cvmx_l2d_bst1_s cn31xx;
@@ -83,8 +94,13 @@ union cvmx_l2d_bst1 {
 union cvmx_l2d_bst2 {
 	uint64_t u64;
 	struct cvmx_l2d_bst2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q2stat:34;
+#else
+		uint64_t q2stat:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_bst2_s cn30xx;
 	struct cvmx_l2d_bst2_s cn31xx;
@@ -102,8 +118,13 @@ union cvmx_l2d_bst2 {
 union cvmx_l2d_bst3 {
 	uint64_t u64;
 	struct cvmx_l2d_bst3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q3stat:34;
+#else
+		uint64_t q3stat:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_bst3_s cn30xx;
 	struct cvmx_l2d_bst3_s cn31xx;
@@ -121,6 +142,7 @@ union cvmx_l2d_bst3 {
 union cvmx_l2d_err {
 	uint64_t u64;
 	struct cvmx_l2d_err_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_6_63:58;
 		uint64_t bmhclsel:1;
 		uint64_t ded_err:1;
@@ -128,6 +150,15 @@ union cvmx_l2d_err {
 		uint64_t ded_intena:1;
 		uint64_t sec_intena:1;
 		uint64_t ecc_ena:1;
+#else
+		uint64_t ecc_ena:1;
+		uint64_t sec_intena:1;
+		uint64_t ded_intena:1;
+		uint64_t sec_err:1;
+		uint64_t ded_err:1;
+		uint64_t bmhclsel:1;
+		uint64_t reserved_6_63:58;
+#endif
 	} s;
 	struct cvmx_l2d_err_s cn30xx;
 	struct cvmx_l2d_err_s cn31xx;
@@ -145,48 +176,97 @@ union cvmx_l2d_err {
 union cvmx_l2d_fadr {
 	uint64_t u64;
 	struct cvmx_l2d_fadr_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_19_63:45;
 		uint64_t fadru:1;
 		uint64_t fowmsk:4;
 		uint64_t fset:3;
 		uint64_t fadr:11;
+#else
+		uint64_t fadr:11;
+		uint64_t fset:3;
+		uint64_t fowmsk:4;
+		uint64_t fadru:1;
+		uint64_t reserved_19_63:45;
+#endif
 	} s;
 	struct cvmx_l2d_fadr_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t fowmsk:4;
 		uint64_t reserved_13_13:1;
 		uint64_t fset:2;
 		uint64_t reserved_9_10:2;
 		uint64_t fadr:9;
+#else
+		uint64_t fadr:9;
+		uint64_t reserved_9_10:2;
+		uint64_t fset:2;
+		uint64_t reserved_13_13:1;
+		uint64_t fowmsk:4;
+		uint64_t reserved_18_63:46;
+#endif
 	} cn30xx;
 	struct cvmx_l2d_fadr_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t fowmsk:4;
 		uint64_t reserved_13_13:1;
 		uint64_t fset:2;
 		uint64_t reserved_10_10:1;
 		uint64_t fadr:10;
+#else
+		uint64_t fadr:10;
+		uint64_t reserved_10_10:1;
+		uint64_t fset:2;
+		uint64_t reserved_13_13:1;
+		uint64_t fowmsk:4;
+		uint64_t reserved_18_63:46;
+#endif
 	} cn31xx;
 	struct cvmx_l2d_fadr_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t fowmsk:4;
 		uint64_t fset:3;
 		uint64_t fadr:11;
+#else
+		uint64_t fadr:11;
+		uint64_t fset:3;
+		uint64_t fowmsk:4;
+		uint64_t reserved_18_63:46;
+#endif
 	} cn38xx;
 	struct cvmx_l2d_fadr_cn38xx cn38xxp2;
 	struct cvmx_l2d_fadr_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t fowmsk:4;
 		uint64_t fset:3;
 		uint64_t reserved_8_10:3;
 		uint64_t fadr:8;
+#else
+		uint64_t fadr:8;
+		uint64_t reserved_8_10:3;
+		uint64_t fset:3;
+		uint64_t fowmsk:4;
+		uint64_t reserved_18_63:46;
+#endif
 	} cn50xx;
 	struct cvmx_l2d_fadr_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_18_63:46;
 		uint64_t fowmsk:4;
 		uint64_t fset:3;
 		uint64_t reserved_10_10:1;
 		uint64_t fadr:10;
+#else
+		uint64_t fadr:10;
+		uint64_t reserved_10_10:1;
+		uint64_t fset:3;
+		uint64_t fowmsk:4;
+		uint64_t reserved_18_63:46;
+#endif
 	} cn52xx;
 	struct cvmx_l2d_fadr_cn52xx cn52xxp1;
 	struct cvmx_l2d_fadr_s cn56xx;
@@ -198,9 +278,15 @@ union cvmx_l2d_fadr {
 union cvmx_l2d_fsyn0 {
 	uint64_t u64;
 	struct cvmx_l2d_fsyn0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_20_63:44;
 		uint64_t fsyn_ow1:10;
 		uint64_t fsyn_ow0:10;
+#else
+		uint64_t fsyn_ow0:10;
+		uint64_t fsyn_ow1:10;
+		uint64_t reserved_20_63:44;
+#endif
 	} s;
 	struct cvmx_l2d_fsyn0_s cn30xx;
 	struct cvmx_l2d_fsyn0_s cn31xx;
@@ -218,9 +304,15 @@ union cvmx_l2d_fsyn0 {
 union cvmx_l2d_fsyn1 {
 	uint64_t u64;
 	struct cvmx_l2d_fsyn1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_20_63:44;
 		uint64_t fsyn_ow3:10;
 		uint64_t fsyn_ow2:10;
+#else
+		uint64_t fsyn_ow2:10;
+		uint64_t fsyn_ow3:10;
+		uint64_t reserved_20_63:44;
+#endif
 	} s;
 	struct cvmx_l2d_fsyn1_s cn30xx;
 	struct cvmx_l2d_fsyn1_s cn31xx;
@@ -238,8 +330,13 @@ union cvmx_l2d_fsyn1 {
 union cvmx_l2d_fus0 {
 	uint64_t u64;
 	struct cvmx_l2d_fus0_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q0fus:34;
+#else
+		uint64_t q0fus:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_fus0_s cn30xx;
 	struct cvmx_l2d_fus0_s cn31xx;
@@ -257,8 +354,13 @@ union cvmx_l2d_fus0 {
 union cvmx_l2d_fus1 {
 	uint64_t u64;
 	struct cvmx_l2d_fus1_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q1fus:34;
+#else
+		uint64_t q1fus:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_fus1_s cn30xx;
 	struct cvmx_l2d_fus1_s cn31xx;
@@ -276,8 +378,13 @@ union cvmx_l2d_fus1 {
 union cvmx_l2d_fus2 {
 	uint64_t u64;
 	struct cvmx_l2d_fus2_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_34_63:30;
 		uint64_t q2fus:34;
+#else
+		uint64_t q2fus:34;
+		uint64_t reserved_34_63:30;
+#endif
 	} s;
 	struct cvmx_l2d_fus2_s cn30xx;
 	struct cvmx_l2d_fus2_s cn31xx;
@@ -295,61 +402,123 @@ union cvmx_l2d_fus2 {
 union cvmx_l2d_fus3 {
 	uint64_t u64;
 	struct cvmx_l2d_fus3_s {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_40_63:24;
 		uint64_t ema_ctl:3;
 		uint64_t reserved_34_36:3;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t reserved_34_36:3;
+		uint64_t ema_ctl:3;
+		uint64_t reserved_40_63:24;
+#endif
 	} s;
 	struct cvmx_l2d_fus3_cn30xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_35_63:29;
 		uint64_t crip_64k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_64k:1;
+		uint64_t reserved_35_63:29;
+#endif
 	} cn30xx;
 	struct cvmx_l2d_fus3_cn31xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_35_63:29;
 		uint64_t crip_128k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_128k:1;
+		uint64_t reserved_35_63:29;
+#endif
 	} cn31xx;
 	struct cvmx_l2d_fus3_cn38xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_36_63:28;
 		uint64_t crip_256k:1;
 		uint64_t crip_512k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_512k:1;
+		uint64_t crip_256k:1;
+		uint64_t reserved_36_63:28;
+#endif
 	} cn38xx;
 	struct cvmx_l2d_fus3_cn38xx cn38xxp2;
 	struct cvmx_l2d_fus3_cn50xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_40_63:24;
 		uint64_t ema_ctl:3;
 		uint64_t reserved_36_36:1;
 		uint64_t crip_32k:1;
 		uint64_t crip_64k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_64k:1;
+		uint64_t crip_32k:1;
+		uint64_t reserved_36_36:1;
+		uint64_t ema_ctl:3;
+		uint64_t reserved_40_63:24;
+#endif
 	} cn50xx;
 	struct cvmx_l2d_fus3_cn52xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_40_63:24;
 		uint64_t ema_ctl:3;
 		uint64_t reserved_36_36:1;
 		uint64_t crip_128k:1;
 		uint64_t crip_256k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_256k:1;
+		uint64_t crip_128k:1;
+		uint64_t reserved_36_36:1;
+		uint64_t ema_ctl:3;
+		uint64_t reserved_40_63:24;
+#endif
 	} cn52xx;
 	struct cvmx_l2d_fus3_cn52xx cn52xxp1;
 	struct cvmx_l2d_fus3_cn56xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_40_63:24;
 		uint64_t ema_ctl:3;
 		uint64_t reserved_36_36:1;
 		uint64_t crip_512k:1;
 		uint64_t crip_1024k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_1024k:1;
+		uint64_t crip_512k:1;
+		uint64_t reserved_36_36:1;
+		uint64_t ema_ctl:3;
+		uint64_t reserved_40_63:24;
+#endif
 	} cn56xx;
 	struct cvmx_l2d_fus3_cn56xx cn56xxp1;
 	struct cvmx_l2d_fus3_cn58xx {
+#ifdef __BIG_ENDIAN_BITFIELD
 		uint64_t reserved_39_63:25;
 		uint64_t ema_ctl:2;
 		uint64_t reserved_36_36:1;
 		uint64_t crip_512k:1;
 		uint64_t crip_1024k:1;
 		uint64_t q3fus:34;
+#else
+		uint64_t q3fus:34;
+		uint64_t crip_1024k:1;
+		uint64_t crip_512k:1;
+		uint64_t reserved_36_36:1;
+		uint64_t ema_ctl:2;
+		uint64_t reserved_39_63:25;
+#endif
 	} cn58xx;
 	struct cvmx_l2d_fus3_cn58xx cn58xxp1;
 };