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| author | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
|---|---|---|
| committer | Michal Marek <mmarek@suse.cz> | 2010-10-12 15:09:06 +0200 |
| commit | 239060b93bb30a4ad55f1ecaa512464a035cc5ba (patch) | |
| tree | 77f79810e57d4fc24356eca0cd6db463e8994128 /arch/mips/include/asm/mach-jz4740/irq.h | |
| parent | 1408b15b98635a13bad2e2a50b3c2ae2ccdf625b (diff) | |
| parent | e9203c988234aa512bd45ca32b52e21c7bbfc414 (diff) | |
| download | op-kernel-dev-239060b93bb30a4ad55f1ecaa512464a035cc5ba.zip op-kernel-dev-239060b93bb30a4ad55f1ecaa512464a035cc5ba.tar.gz | |
Merge branch 'kbuild/rc-fixes' into kbuild/kconfig
We need to revert the temporary hack in 71ebc01, hence the merge.
Diffstat (limited to 'arch/mips/include/asm/mach-jz4740/irq.h')
| -rw-r--r-- | arch/mips/include/asm/mach-jz4740/irq.h | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mach-jz4740/irq.h b/arch/mips/include/asm/mach-jz4740/irq.h new file mode 100644 index 0000000..a865c98 --- /dev/null +++ b/arch/mips/include/asm/mach-jz4740/irq.h @@ -0,0 +1,57 @@ +/* + * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> + * JZ4740 IRQ definitions + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#ifndef __ASM_MACH_JZ4740_IRQ_H__ +#define __ASM_MACH_JZ4740_IRQ_H__ + +#define MIPS_CPU_IRQ_BASE 0 +#define JZ4740_IRQ_BASE 8 + +/* 1st-level interrupts */ +#define JZ4740_IRQ(x) (JZ4740_IRQ_BASE + (x)) +#define JZ4740_IRQ_I2C JZ4740_IRQ(1) +#define JZ4740_IRQ_UHC JZ4740_IRQ(3) +#define JZ4740_IRQ_UART1 JZ4740_IRQ(8) +#define JZ4740_IRQ_UART0 JZ4740_IRQ(9) +#define JZ4740_IRQ_SADC JZ4740_IRQ(12) +#define JZ4740_IRQ_MSC JZ4740_IRQ(14) +#define JZ4740_IRQ_RTC JZ4740_IRQ(15) +#define JZ4740_IRQ_SSI JZ4740_IRQ(16) +#define JZ4740_IRQ_CIM JZ4740_IRQ(17) +#define JZ4740_IRQ_AIC JZ4740_IRQ(18) +#define JZ4740_IRQ_ETH JZ4740_IRQ(19) +#define JZ4740_IRQ_DMAC JZ4740_IRQ(20) +#define JZ4740_IRQ_TCU2 JZ4740_IRQ(21) +#define JZ4740_IRQ_TCU1 JZ4740_IRQ(22) +#define JZ4740_IRQ_TCU0 JZ4740_IRQ(23) +#define JZ4740_IRQ_UDC JZ4740_IRQ(24) +#define JZ4740_IRQ_GPIO3 JZ4740_IRQ(25) +#define JZ4740_IRQ_GPIO2 JZ4740_IRQ(26) +#define JZ4740_IRQ_GPIO1 JZ4740_IRQ(27) +#define JZ4740_IRQ_GPIO0 JZ4740_IRQ(28) +#define JZ4740_IRQ_IPU JZ4740_IRQ(29) +#define JZ4740_IRQ_LCD JZ4740_IRQ(30) + +/* 2nd-level interrupts */ +#define JZ4740_IRQ_DMA(x) (JZ4740_IRQ(32) + (X)) + +#define JZ4740_IRQ_INTC_GPIO(x) (JZ4740_IRQ_GPIO0 - (x)) +#define JZ4740_IRQ_GPIO(x) (JZ4740_IRQ(48) + (x)) + +#define JZ4740_IRQ_ADC_BASE JZ4740_IRQ(176) + +#define NR_IRQS (JZ4740_IRQ_ADC_BASE + 6) + +#endif |
