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author | Florian Fainelli <f.fainelli@gmail.com> | 2015-04-07 13:34:00 -0700 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 23:52:32 +0200 |
commit | 36fe97635826d54d07c51a5953148235b7dd6a04 (patch) | |
tree | 0c73ddd2fcb135be088be7b1bd2a4a88f911c008 /arch/mips/include/asm/mach-bmips/dma-coherence.h | |
parent | 87842661a315618dfdeeede188257e4011164023 (diff) | |
download | op-kernel-dev-36fe97635826d54d07c51a5953148235b7dd6a04.zip op-kernel-dev-36fe97635826d54d07c51a5953148235b7dd6a04.tar.gz |
MIPS: BMIPS: Move post DMA flush implementation to common header
arch/mips/include/asm/mach-bmips/dma-coherence.h contains the
plat_post_dma_flush implementation which is not specific to mach-bmips,
but required for all BMIPS-based systems.
Move plat_post_dma_flush to arch/mips/include/asm/bmips.h, rename it to
bmips_post_dma_flush such that other platforms like bcm63xx can utilize
it.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: cernekee@gmail.com
Cc: jogo@openwrt.org
Patchwork: https://patchwork.linux-mips.org/patch/9724/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-bmips/dma-coherence.h')
-rw-r--r-- | arch/mips/include/asm/mach-bmips/dma-coherence.h | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/arch/mips/include/asm/mach-bmips/dma-coherence.h b/arch/mips/include/asm/mach-bmips/dma-coherence.h index ee3c713..d29781f 100644 --- a/arch/mips/include/asm/mach-bmips/dma-coherence.h +++ b/arch/mips/include/asm/mach-bmips/dma-coherence.h @@ -49,20 +49,6 @@ static inline int plat_device_is_coherent(struct device *dev) return 0; } -static inline void plat_post_dma_flush(struct device *dev) -{ - void __iomem *cbr = BMIPS_GET_CBR(); - u32 cfg; - - if (boot_cpu_type() != CPU_BMIPS3300 && - boot_cpu_type() != CPU_BMIPS4350 && - boot_cpu_type() != CPU_BMIPS4380) - return; - - /* Flush stale data out of the readahead cache */ - cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG); - __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG); - __raw_readl(cbr + BMIPS_RAC_CONFIG); -} +#define plat_post_dma_flush bmips_post_dma_flush #endif /* __ASM_MACH_BMIPS_DMA_COHERENCE_H */ |