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author | David Daney <david.daney@cavium.com> | 2014-05-28 23:52:07 +0200 |
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committer | Ralf Baechle <ralf@linux-mips.org> | 2014-05-30 21:01:10 +0200 |
commit | a68d09a156b2a543117bb98df4c8c4cd1b857124 (patch) | |
tree | ea07a66f98fa9ae798b4e9974e7fd5146d60a2c2 /arch/mips/include/asm/cpu-features.h | |
parent | 8a837cdb0a51c4b45aca8966cf11af99b397c97d (diff) | |
download | op-kernel-dev-a68d09a156b2a543117bb98df4c8c4cd1b857124.zip op-kernel-dev-a68d09a156b2a543117bb98df4c8c4cd1b857124.tar.gz |
MIPS: Don't use RI/XI with 32-bit kernels on 64-bit CPUs
The TLB handlers cannot handle this case, so disable it for now.
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com>
Cc: linux-mips@linux-mips.org
Cc: James Hogan <james.hogan@imgtec.com>
Cc: kvm@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/7007/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/cpu-features.h')
-rw-r--r-- | arch/mips/include/asm/cpu-features.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index f75dd70..c7d8c99 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -110,9 +110,15 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif + #ifndef cpu_has_rixi -#define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# ifdef CONFIG_64BIT +# define cpu_has_rixi (cpu_data[0].options & MIPS_CPU_RIXI) +# else /* CONFIG_32BIT */ +# define cpu_has_rixi ((cpu_data[0].options & MIPS_CPU_RIXI) && !cpu_has_64bits) +# endif #endif + #ifndef cpu_has_mmips # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS # define cpu_has_mmips (cpu_data[0].options & MIPS_CPU_MICROMIPS) @@ -120,6 +126,7 @@ # define cpu_has_mmips 0 # endif #endif + #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif |