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authorHuacai Chen <chenhc@lemote.com>2014-01-14 17:56:37 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2014-01-15 14:19:42 +0700
commitbad009fe354a00e6b2bf87328995ec76e59ab970 (patch)
tree842f0a9b39820d7e0d2ea5a0a462bbaa4a916826 /arch/mips/include/asm/cacheops.h
parent70f2fe3a26248724d8a5019681a869abdaf3e89a (diff)
downloadop-kernel-dev-bad009fe354a00e6b2bf87328995ec76e59ab970.zip
op-kernel-dev-bad009fe354a00e6b2bf87328995ec76e59ab970.tar.gz
MIPS: fix case mismatch in local_r4k_flush_icache_range()
Currently, Loongson-2 call protected_blast_icache_range() and others call protected_loongson23_blast_icache_range(), but I think the correct behavior should be the opposite. BTW, Loongson-3's cache-ops is compatible with MIPS64, but not compatible with Loongson-2. So, rename xxx_loongson23_yyy things to xxx_loongson2_yyy. The patch fixes early boot hang with 3.13-rc1, introduced in commit 14bd8c082016 ("MIPS: Loongson: Get rid of Loongson 2 #ifdefery all over arch/mips"). Signed-off-by: Huacai Chen <chenhc@lemote.com> Signed-off-by: Aaro Koskinen <aaro.koskinen@iki.fi> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: John Crispin <blogic@openwrt.org> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/mips/include/asm/cacheops.h')
-rw-r--r--arch/mips/include/asm/cacheops.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index c75025f..06b9bc7 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -83,6 +83,6 @@
/*
* Loongson2-specific cacheops
*/
-#define Hit_Invalidate_I_Loongson23 0x00
+#define Hit_Invalidate_I_Loongson2 0x00
#endif /* __ASM_CACHEOPS_H */
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